Search

John D. Lee

Examiner (ID: 17114)

Most Active Art Unit
2501
Art Unit(s)
2874, 2606, 2507, 2501, 2504, 3621
Total Applications
2783
Issued Applications
2467
Pending Applications
118
Abandoned Applications
198

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 447724 [patent_doc_number] => 07253502 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-07 [patent_title] => 'Circuitized substrate with internal organic memory device, electrical assembly utilizing same, and information handling system utilizing same' [patent_app_type] => utility [patent_app_number] => 10/900385 [patent_app_country] => US [patent_app_date] => 2004-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 8228 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/253/07253502.pdf [firstpage_image] =>[orig_patent_app_number] => 10900385 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/900385
Circuitized substrate with internal organic memory device, electrical assembly utilizing same, and information handling system utilizing same Jul 27, 2004 Issued
Array ( [id] => 421845 [patent_doc_number] => 07273776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-25 [patent_title] => 'Methods of forming a P-well in an integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/899596 [patent_app_country] => US [patent_app_date] => 2004-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4037 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/273/07273776.pdf [firstpage_image] =>[orig_patent_app_number] => 10899596 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/899596
Methods of forming a P-well in an integrated circuit device Jul 26, 2004 Issued
Array ( [id] => 5768003 [patent_doc_number] => 20060019435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-26 [patent_title] => 'Methods of fabricating nitride-based transistors with a cap layer and a recessed gate' [patent_app_type] => utility [patent_app_number] => 10/897726 [patent_app_country] => US [patent_app_date] => 2004-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7147 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20060019435.pdf [firstpage_image] =>[orig_patent_app_number] => 10897726 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/897726
Methods of fabricating nitride-based transistors with a cap layer and a recessed gate Jul 22, 2004 Issued
Array ( [id] => 7061265 [patent_doc_number] => 20050003626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Control of buried oxide in SIMOX' [patent_app_type] => utility [patent_app_number] => 10/896812 [patent_app_country] => US [patent_app_date] => 2004-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3953 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20050003626.pdf [firstpage_image] =>[orig_patent_app_number] => 10896812 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/896812
Control of buried oxide in SIMOX Jul 21, 2004 Issued
Array ( [id] => 7022901 [patent_doc_number] => 20050017295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Semiconductor devices having a buried and enlarged contact hole and methods of fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/898485 [patent_app_country] => US [patent_app_date] => 2004-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 3541 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20050017295.pdf [firstpage_image] =>[orig_patent_app_number] => 10898485 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/898485
Method of fabricating a semiconductor device having a buried and enlarged contact hole Jul 21, 2004 Issued
Array ( [id] => 909980 [patent_doc_number] => 07329555 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-02-12 [patent_title] => 'Method of selectively forming MEMS-based semiconductor devices at the end of a common fabrication process' [patent_app_type] => utility [patent_app_number] => 10/894846 [patent_app_country] => US [patent_app_date] => 2004-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 1994 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/329/07329555.pdf [firstpage_image] =>[orig_patent_app_number] => 10894846 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/894846
Method of selectively forming MEMS-based semiconductor devices at the end of a common fabrication process Jul 19, 2004 Issued
Array ( [id] => 934026 [patent_doc_number] => 06977221 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-20 [patent_title] => 'Methods of forming an electrically conductive line' [patent_app_type] => utility [patent_app_number] => 10/895483 [patent_app_country] => US [patent_app_date] => 2004-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 3865 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/977/06977221.pdf [firstpage_image] =>[orig_patent_app_number] => 10895483 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/895483
Methods of forming an electrically conductive line Jul 19, 2004 Issued
Array ( [id] => 616375 [patent_doc_number] => 07144786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-05 [patent_title] => 'Technique for forming a transistor having raised drain and source regions with a reduced number of process steps' [patent_app_type] => utility [patent_app_number] => 10/891996 [patent_app_country] => US [patent_app_date] => 2004-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 7255 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/144/07144786.pdf [firstpage_image] =>[orig_patent_app_number] => 10891996 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/891996
Technique for forming a transistor having raised drain and source regions with a reduced number of process steps Jul 14, 2004 Issued
Array ( [id] => 7025637 [patent_doc_number] => 20050020031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Methods for preparing a semiconductor assembly' [patent_app_type] => utility [patent_app_number] => 10/893596 [patent_app_country] => US [patent_app_date] => 2004-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3952 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20050020031.pdf [firstpage_image] =>[orig_patent_app_number] => 10893596 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/893596
Methods for preparing a semiconductor assembly Jul 14, 2004 Issued
Array ( [id] => 7264012 [patent_doc_number] => 20040241905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'Apparatus and method for attaching an integrated circuit sensor to a substrate' [patent_app_type] => new [patent_app_number] => 10/889725 [patent_app_country] => US [patent_app_date] => 2004-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2008 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20040241905.pdf [firstpage_image] =>[orig_patent_app_number] => 10889725 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/889725
Apparatus and method for attaching an integrating circuit sensor to a substrate Jul 12, 2004 Issued
Array ( [id] => 679655 [patent_doc_number] => 07084025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Selective oxide trimming to improve metal T-gate transistor' [patent_app_type] => utility [patent_app_number] => 10/885855 [patent_app_country] => US [patent_app_date] => 2004-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 33 [patent_no_of_words] => 5167 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084025.pdf [firstpage_image] =>[orig_patent_app_number] => 10885855 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/885855
Selective oxide trimming to improve metal T-gate transistor Jul 6, 2004 Issued
Array ( [id] => 7348839 [patent_doc_number] => 20040248331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Methods for producing optoelectronic devices' [patent_app_type] => new [patent_app_number] => 10/884895 [patent_app_country] => US [patent_app_date] => 2004-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5775 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20040248331.pdf [firstpage_image] =>[orig_patent_app_number] => 10884895 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/884895
Method for forming an optoelectronic device having an isolation layer Jul 5, 2004 Issued
Array ( [id] => 5892617 [patent_doc_number] => 20060001154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Chip-to-chip trench circuit structure' [patent_app_type] => utility [patent_app_number] => 10/883356 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2242 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20060001154.pdf [firstpage_image] =>[orig_patent_app_number] => 10883356 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/883356
Chip-to-chip trench circuit structure Jun 29, 2004 Issued
Array ( [id] => 612702 [patent_doc_number] => 07148099 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-12 [patent_title] => 'Reducing the dielectric constant of a portion of a gate dielectric' [patent_app_type] => utility [patent_app_number] => 10/877836 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4924 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/148/07148099.pdf [firstpage_image] =>[orig_patent_app_number] => 10877836 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/877836
Reducing the dielectric constant of a portion of a gate dielectric Jun 23, 2004 Issued
Array ( [id] => 5239831 [patent_doc_number] => 20070018322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Wafer level package and its manufacturing method' [patent_app_type] => utility [patent_app_number] => 10/876196 [patent_app_country] => US [patent_app_date] => 2004-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2638 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20070018322.pdf [firstpage_image] =>[orig_patent_app_number] => 10876196 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/876196
Wafer level package and its manufacturing method Jun 22, 2004 Abandoned
Array ( [id] => 496694 [patent_doc_number] => 07208346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-24 [patent_title] => 'Methods of forming interposers on surfaces of dies of a wafer' [patent_app_type] => utility [patent_app_number] => 10/867446 [patent_app_country] => US [patent_app_date] => 2004-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 3866 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/208/07208346.pdf [firstpage_image] =>[orig_patent_app_number] => 10867446 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/867446
Methods of forming interposers on surfaces of dies of a wafer Jun 13, 2004 Issued
Array ( [id] => 1024599 [patent_doc_number] => 06884715 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-26 [patent_title] => 'Method for forming a self-aligned contact with a silicide or damascene conductor and the structure formed thereby' [patent_app_type] => utility [patent_app_number] => 10/709906 [patent_app_country] => US [patent_app_date] => 2004-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 37 [patent_no_of_words] => 8493 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/884/06884715.pdf [firstpage_image] =>[orig_patent_app_number] => 10709906 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/709906
Method for forming a self-aligned contact with a silicide or damascene conductor and the structure formed thereby Jun 3, 2004 Issued
Array ( [id] => 7058936 [patent_doc_number] => 20050001295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Adhesion enhanced semiconductor die for mold compound packaging' [patent_app_type] => utility [patent_app_number] => 10/852632 [patent_app_country] => US [patent_app_date] => 2004-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1931 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20050001295.pdf [firstpage_image] =>[orig_patent_app_number] => 10852632 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/852632
Adhesion enhanced semiconductor die for mold compound packaging May 23, 2004 Abandoned
Array ( [id] => 7291855 [patent_doc_number] => 20040212092 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Methods of fabricating semiconductor substrate-based BGA interconnections' [patent_app_type] => new [patent_app_number] => 10/848762 [patent_app_country] => US [patent_app_date] => 2004-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4571 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0212/20040212092.pdf [firstpage_image] =>[orig_patent_app_number] => 10848762 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/848762
Semiconductor substrate-based interconnection assembly for semiconductor device bearing external connection elements May 17, 2004 Issued
Array ( [id] => 7184270 [patent_doc_number] => 20040203230 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-14 [patent_title] => 'Semiconductor device having multilayered conductive layers' [patent_app_type] => new [patent_app_number] => 10/834126 [patent_app_country] => US [patent_app_date] => 2004-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3580 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20040203230.pdf [firstpage_image] =>[orig_patent_app_number] => 10834126 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/834126
Semiconductor device having multilayered conductive layers Apr 28, 2004 Abandoned
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