
John D. Lee
Examiner (ID: 17114)
| Most Active Art Unit | 2501 |
| Art Unit(s) | 2874, 2606, 2507, 2501, 2504, 3621 |
| Total Applications | 2783 |
| Issued Applications | 2467 |
| Pending Applications | 118 |
| Abandoned Applications | 198 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 447724
[patent_doc_number] => 07253502
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-08-07
[patent_title] => 'Circuitized substrate with internal organic memory device, electrical assembly utilizing same, and information handling system utilizing same'
[patent_app_type] => utility
[patent_app_number] => 10/900385
[patent_app_country] => US
[patent_app_date] => 2004-07-28
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/253/07253502.pdf
[firstpage_image] =>[orig_patent_app_number] => 10900385
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/900385 | Circuitized substrate with internal organic memory device, electrical assembly utilizing same, and information handling system utilizing same | Jul 27, 2004 | Issued |
Array
(
[id] => 421845
[patent_doc_number] => 07273776
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-25
[patent_title] => 'Methods of forming a P-well in an integrated circuit device'
[patent_app_type] => utility
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[patent_app_country] => US
[patent_app_date] => 2004-07-27
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[firstpage_image] =>[orig_patent_app_number] => 10899596
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/899596 | Methods of forming a P-well in an integrated circuit device | Jul 26, 2004 | Issued |
Array
(
[id] => 5768003
[patent_doc_number] => 20060019435
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[patent_kind] => A1
[patent_issue_date] => 2006-01-26
[patent_title] => 'Methods of fabricating nitride-based transistors with a cap layer and a recessed gate'
[patent_app_type] => utility
[patent_app_number] => 10/897726
[patent_app_country] => US
[patent_app_date] => 2004-07-23
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Array
(
[id] => 7061265
[patent_doc_number] => 20050003626
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[patent_kind] => A1
[patent_issue_date] => 2005-01-06
[patent_title] => 'Control of buried oxide in SIMOX'
[patent_app_type] => utility
[patent_app_number] => 10/896812
[patent_app_country] => US
[patent_app_date] => 2004-07-22
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/896812 | Control of buried oxide in SIMOX | Jul 21, 2004 | Issued |
Array
(
[id] => 7022901
[patent_doc_number] => 20050017295
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[patent_kind] => A1
[patent_issue_date] => 2005-01-27
[patent_title] => 'Semiconductor devices having a buried and enlarged contact hole and methods of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 10/898485
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[patent_app_date] => 2004-07-22
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/898485 | Method of fabricating a semiconductor device having a buried and enlarged contact hole | Jul 21, 2004 | Issued |
Array
(
[id] => 909980
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[patent_issue_date] => 2008-02-12
[patent_title] => 'Method of selectively forming MEMS-based semiconductor devices at the end of a common fabrication process'
[patent_app_type] => utility
[patent_app_number] => 10/894846
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/894846 | Method of selectively forming MEMS-based semiconductor devices at the end of a common fabrication process | Jul 19, 2004 | Issued |
Array
(
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[patent_doc_number] => 06977221
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[patent_issue_date] => 2005-12-20
[patent_title] => 'Methods of forming an electrically conductive line'
[patent_app_type] => utility
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[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10895483
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/895483 | Methods of forming an electrically conductive line | Jul 19, 2004 | Issued |
Array
(
[id] => 616375
[patent_doc_number] => 07144786
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[patent_kind] => B2
[patent_issue_date] => 2006-12-05
[patent_title] => 'Technique for forming a transistor having raised drain and source regions with a reduced number of process steps'
[patent_app_type] => utility
[patent_app_number] => 10/891996
[patent_app_country] => US
[patent_app_date] => 2004-07-15
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[firstpage_image] =>[orig_patent_app_number] => 10891996
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/891996 | Technique for forming a transistor having raised drain and source regions with a reduced number of process steps | Jul 14, 2004 | Issued |
Array
(
[id] => 7025637
[patent_doc_number] => 20050020031
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[patent_issue_date] => 2005-01-27
[patent_title] => 'Methods for preparing a semiconductor assembly'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/893596 | Methods for preparing a semiconductor assembly | Jul 14, 2004 | Issued |
Array
(
[id] => 7264012
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[patent_issue_date] => 2004-12-02
[patent_title] => 'Apparatus and method for attaching an integrated circuit sensor to a substrate'
[patent_app_type] => new
[patent_app_number] => 10/889725
[patent_app_country] => US
[patent_app_date] => 2004-07-13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/889725 | Apparatus and method for attaching an integrating circuit sensor to a substrate | Jul 12, 2004 | Issued |
Array
(
[id] => 679655
[patent_doc_number] => 07084025
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[patent_title] => 'Selective oxide trimming to improve metal T-gate transistor'
[patent_app_type] => utility
[patent_app_number] => 10/885855
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Array
(
[id] => 7348839
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[patent_issue_date] => 2004-12-09
[patent_title] => 'Methods for producing optoelectronic devices'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/884895 | Method for forming an optoelectronic device having an isolation layer | Jul 5, 2004 | Issued |
Array
(
[id] => 5892617
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[patent_title] => 'Chip-to-chip trench circuit structure'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/883356 | Chip-to-chip trench circuit structure | Jun 29, 2004 | Issued |
Array
(
[id] => 612702
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[patent_title] => 'Reducing the dielectric constant of a portion of a gate dielectric'
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Array
(
[id] => 5239831
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[patent_title] => 'Wafer level package and its manufacturing method'
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[firstpage_image] =>[orig_patent_app_number] => 10876196
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/876196 | Wafer level package and its manufacturing method | Jun 22, 2004 | Abandoned |
Array
(
[id] => 496694
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/867446 | Methods of forming interposers on surfaces of dies of a wafer | Jun 13, 2004 | Issued |
Array
(
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[patent_title] => 'Method for forming a self-aligned contact with a silicide or damascene conductor and the structure formed thereby'
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Array
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Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/834126 | Semiconductor device having multilayered conductive layers | Apr 28, 2004 | Abandoned |