
John D. Lee
Examiner (ID: 17114)
| Most Active Art Unit | 2501 |
| Art Unit(s) | 2874, 2606, 2507, 2501, 2504, 3621 |
| Total Applications | 2783 |
| Issued Applications | 2467 |
| Pending Applications | 118 |
| Abandoned Applications | 198 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7069689
[patent_doc_number] => 20050245074
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-03
[patent_title] => 'In-situ etch-stop etch and ashing in association with damascene processing in forming semiconductor interconnect structures'
[patent_app_type] => utility
[patent_app_number] => 10/834436
[patent_app_country] => US
[patent_app_date] => 2004-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 10120
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0245/20050245074.pdf
[firstpage_image] =>[orig_patent_app_number] => 10834436
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/834436 | In-situ etch-stop etch and ashing in association with damascene processing in forming semiconductor interconnect structures | Apr 28, 2004 | Abandoned |
Array
(
[id] => 860213
[patent_doc_number] => 07371607
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-05-13
[patent_title] => 'Method of manufacturing semiconductor device and method of manufacturing electronic device'
[patent_app_type] => utility
[patent_app_number] => 10/833945
[patent_app_country] => US
[patent_app_date] => 2004-04-28
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[pdf_file] => patents/07/371/07371607.pdf
[firstpage_image] =>[orig_patent_app_number] => 10833945
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/833945 | Method of manufacturing semiconductor device and method of manufacturing electronic device | Apr 27, 2004 | Issued |
Array
(
[id] => 721337
[patent_doc_number] => 07049703
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[patent_kind] => B2
[patent_issue_date] => 2006-05-23
[patent_title] => 'Semiconductor device having a tapered interconnection with insulating material on conductive sidewall thereof within through hole'
[patent_app_type] => utility
[patent_app_number] => 10/832229
[patent_app_country] => US
[patent_app_date] => 2004-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/832229 | Semiconductor device having a tapered interconnection with insulating material on conductive sidewall thereof within through hole | Apr 26, 2004 | Issued |
Array
(
[id] => 620449
[patent_doc_number] => 07141866
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-11-28
[patent_title] => 'Apparatus for imprinting lithography and fabrication thereof'
[patent_app_type] => utility
[patent_app_number] => 10/826056
[patent_app_country] => US
[patent_app_date] => 2004-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 7860
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/826056 | Apparatus for imprinting lithography and fabrication thereof | Apr 15, 2004 | Issued |
Array
(
[id] => 448426
[patent_doc_number] => 07250319
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[patent_kind] => B2
[patent_issue_date] => 2007-07-31
[patent_title] => 'Method of fabricating quantum features'
[patent_app_type] => utility
[patent_app_number] => 10/825826
[patent_app_country] => US
[patent_app_date] => 2004-04-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/250/07250319.pdf
[firstpage_image] =>[orig_patent_app_number] => 10825826
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/825826 | Method of fabricating quantum features | Apr 15, 2004 | Issued |
Array
(
[id] => 7442517
[patent_doc_number] => 20040185609
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[patent_issue_date] => 2004-09-23
[patent_title] => 'Semiconductor manufacturing method including forming additional active layer'
[patent_app_type] => new
[patent_app_number] => 10/814270
[patent_app_country] => US
[patent_app_date] => 2004-04-01
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[firstpage_image] =>[orig_patent_app_number] => 10814270
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/814270 | Semiconductor manufacturing method including forming additional active layer | Mar 31, 2004 | Abandoned |
Array
(
[id] => 6949857
[patent_doc_number] => 20050224951
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[patent_kind] => A1
[patent_issue_date] => 2005-10-13
[patent_title] => 'Jet-dispensed stress relief layer in contact arrays, and processes of making same'
[patent_app_type] => utility
[patent_app_number] => 10/815565
[patent_app_country] => US
[patent_app_date] => 2004-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 6480
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[firstpage_image] =>[orig_patent_app_number] => 10815565
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/815565 | Jet-dispensed stress relief layer in contact arrays, and processes of making same | Mar 30, 2004 | Abandoned |
Array
(
[id] => 623585
[patent_doc_number] => 07138313
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[patent_kind] => B2
[patent_issue_date] => 2006-11-21
[patent_title] => 'Method for creating a self-aligned SOI diode by removing a polysilicon gate during processing'
[patent_app_type] => utility
[patent_app_number] => 10/708912
[patent_app_country] => US
[patent_app_date] => 2004-03-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 3259
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[pdf_file] => patents/07/138/07138313.pdf
[firstpage_image] =>[orig_patent_app_number] => 10708912
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/708912 | Method for creating a self-aligned SOI diode by removing a polysilicon gate during processing | Mar 30, 2004 | Issued |
Array
(
[id] => 485609
[patent_doc_number] => 07217638
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-15
[patent_title] => 'Wafer back surface treating method and dicing sheet adhering apparatus'
[patent_app_type] => utility
[patent_app_number] => 10/809566
[patent_app_country] => US
[patent_app_date] => 2004-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/07/217/07217638.pdf
[firstpage_image] =>[orig_patent_app_number] => 10809566
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/809566 | Wafer back surface treating method and dicing sheet adhering apparatus | Mar 24, 2004 | Issued |
Array
(
[id] => 7111310
[patent_doc_number] => 20050208766
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[patent_kind] => A1
[patent_issue_date] => 2005-09-22
[patent_title] => 'Etch solution for selectively removing silicon and methods of selectively removing silicon'
[patent_app_type] => utility
[patent_app_number] => 10/804366
[patent_app_country] => US
[patent_app_date] => 2004-03-19
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[patent_drawing_sheets_cnt] => 5
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[firstpage_image] =>[orig_patent_app_number] => 10804366
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/804366 | Methods of selectively removing silicon | Mar 18, 2004 | Issued |
Array
(
[id] => 7406888
[patent_doc_number] => 20040175938
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[patent_title] => 'Method for metalizing wafers'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/803765 | Method for metalizing wafers | Mar 17, 2004 | Abandoned |
Array
(
[id] => 7025665
[patent_doc_number] => 20050020059
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[patent_title] => 'Method for forming aluminum-containing interconnect'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/800695 | Method for forming aluminum-containing interconnect | Mar 15, 2004 | Abandoned |
Array
(
[id] => 7363359
[patent_doc_number] => 20040217462
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[patent_issue_date] => 2004-11-04
[patent_title] => 'Semiconductor device and process for fabrication of the same'
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Array
(
[id] => 7114393
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Array
(
[id] => 493675
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Array
(
[id] => 7344332
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Array
(
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Array
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Array
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Array
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