Search

John D. Lee

Examiner (ID: 17114)

Most Active Art Unit
2501
Art Unit(s)
2874, 2606, 2507, 2501, 2504, 3621
Total Applications
2783
Issued Applications
2467
Pending Applications
118
Abandoned Applications
198

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7069689 [patent_doc_number] => 20050245074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-03 [patent_title] => 'In-situ etch-stop etch and ashing in association with damascene processing in forming semiconductor interconnect structures' [patent_app_type] => utility [patent_app_number] => 10/834436 [patent_app_country] => US [patent_app_date] => 2004-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10120 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20050245074.pdf [firstpage_image] =>[orig_patent_app_number] => 10834436 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/834436
In-situ etch-stop etch and ashing in association with damascene processing in forming semiconductor interconnect structures Apr 28, 2004 Abandoned
Array ( [id] => 860213 [patent_doc_number] => 07371607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-13 [patent_title] => 'Method of manufacturing semiconductor device and method of manufacturing electronic device' [patent_app_type] => utility [patent_app_number] => 10/833945 [patent_app_country] => US [patent_app_date] => 2004-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 6362 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/371/07371607.pdf [firstpage_image] =>[orig_patent_app_number] => 10833945 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/833945
Method of manufacturing semiconductor device and method of manufacturing electronic device Apr 27, 2004 Issued
Array ( [id] => 721337 [patent_doc_number] => 07049703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-23 [patent_title] => 'Semiconductor device having a tapered interconnection with insulating material on conductive sidewall thereof within through hole' [patent_app_type] => utility [patent_app_number] => 10/832229 [patent_app_country] => US [patent_app_date] => 2004-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 36 [patent_no_of_words] => 6667 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/049/07049703.pdf [firstpage_image] =>[orig_patent_app_number] => 10832229 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/832229
Semiconductor device having a tapered interconnection with insulating material on conductive sidewall thereof within through hole Apr 26, 2004 Issued
Array ( [id] => 620449 [patent_doc_number] => 07141866 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-11-28 [patent_title] => 'Apparatus for imprinting lithography and fabrication thereof' [patent_app_type] => utility [patent_app_number] => 10/826056 [patent_app_country] => US [patent_app_date] => 2004-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 7860 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/141/07141866.pdf [firstpage_image] =>[orig_patent_app_number] => 10826056 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/826056
Apparatus for imprinting lithography and fabrication thereof Apr 15, 2004 Issued
Array ( [id] => 448426 [patent_doc_number] => 07250319 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-31 [patent_title] => 'Method of fabricating quantum features' [patent_app_type] => utility [patent_app_number] => 10/825826 [patent_app_country] => US [patent_app_date] => 2004-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 5103 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/250/07250319.pdf [firstpage_image] =>[orig_patent_app_number] => 10825826 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/825826
Method of fabricating quantum features Apr 15, 2004 Issued
Array ( [id] => 7442517 [patent_doc_number] => 20040185609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'Semiconductor manufacturing method including forming additional active layer' [patent_app_type] => new [patent_app_number] => 10/814270 [patent_app_country] => US [patent_app_date] => 2004-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8116 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20040185609.pdf [firstpage_image] =>[orig_patent_app_number] => 10814270 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/814270
Semiconductor manufacturing method including forming additional active layer Mar 31, 2004 Abandoned
Array ( [id] => 6949857 [patent_doc_number] => 20050224951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Jet-dispensed stress relief layer in contact arrays, and processes of making same' [patent_app_type] => utility [patent_app_number] => 10/815565 [patent_app_country] => US [patent_app_date] => 2004-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6480 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20050224951.pdf [firstpage_image] =>[orig_patent_app_number] => 10815565 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/815565
Jet-dispensed stress relief layer in contact arrays, and processes of making same Mar 30, 2004 Abandoned
Array ( [id] => 623585 [patent_doc_number] => 07138313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-21 [patent_title] => 'Method for creating a self-aligned SOI diode by removing a polysilicon gate during processing' [patent_app_type] => utility [patent_app_number] => 10/708912 [patent_app_country] => US [patent_app_date] => 2004-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/138/07138313.pdf [firstpage_image] =>[orig_patent_app_number] => 10708912 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/708912
Method for creating a self-aligned SOI diode by removing a polysilicon gate during processing Mar 30, 2004 Issued
Array ( [id] => 485609 [patent_doc_number] => 07217638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-15 [patent_title] => 'Wafer back surface treating method and dicing sheet adhering apparatus' [patent_app_type] => utility [patent_app_number] => 10/809566 [patent_app_country] => US [patent_app_date] => 2004-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5360 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/217/07217638.pdf [firstpage_image] =>[orig_patent_app_number] => 10809566 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/809566
Wafer back surface treating method and dicing sheet adhering apparatus Mar 24, 2004 Issued
Array ( [id] => 7111310 [patent_doc_number] => 20050208766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Etch solution for selectively removing silicon and methods of selectively removing silicon' [patent_app_type] => utility [patent_app_number] => 10/804366 [patent_app_country] => US [patent_app_date] => 2004-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5709 [patent_no_of_claims] => 67 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20050208766.pdf [firstpage_image] =>[orig_patent_app_number] => 10804366 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/804366
Methods of selectively removing silicon Mar 18, 2004 Issued
Array ( [id] => 7406888 [patent_doc_number] => 20040175938 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Method for metalizing wafers' [patent_app_type] => new [patent_app_number] => 10/803765 [patent_app_country] => US [patent_app_date] => 2004-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2912 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20040175938.pdf [firstpage_image] =>[orig_patent_app_number] => 10803765 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/803765
Method for metalizing wafers Mar 17, 2004 Abandoned
Array ( [id] => 7025665 [patent_doc_number] => 20050020059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Method for forming aluminum-containing interconnect' [patent_app_type] => utility [patent_app_number] => 10/800695 [patent_app_country] => US [patent_app_date] => 2004-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1484 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20050020059.pdf [firstpage_image] =>[orig_patent_app_number] => 10800695 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/800695
Method for forming aluminum-containing interconnect Mar 15, 2004 Abandoned
Array ( [id] => 7363359 [patent_doc_number] => 20040217462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Semiconductor device and process for fabrication of the same' [patent_app_type] => new [patent_app_number] => 10/799715 [patent_app_country] => US [patent_app_date] => 2004-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 14019 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20040217462.pdf [firstpage_image] =>[orig_patent_app_number] => 10799715 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/799715
Semiconductor device and process for fabrication of the same Mar 14, 2004 Abandoned
Array ( [id] => 7114393 [patent_doc_number] => 20050067693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 10/796146 [patent_app_country] => US [patent_app_date] => 2004-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8723 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20050067693.pdf [firstpage_image] =>[orig_patent_app_number] => 10796146 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/796146
Semiconductor device and manufacturing method thereof Mar 9, 2004 Issued
Array ( [id] => 493675 [patent_doc_number] => 07211511 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-01 [patent_title] => 'Method for manufacturing a magnetic memory device' [patent_app_type] => utility [patent_app_number] => 10/796655 [patent_app_country] => US [patent_app_date] => 2004-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 35 [patent_no_of_words] => 11447 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/211/07211511.pdf [firstpage_image] =>[orig_patent_app_number] => 10796655 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/796655
Method for manufacturing a magnetic memory device Mar 8, 2004 Issued
Array ( [id] => 7344332 [patent_doc_number] => 20040192047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-30 [patent_title] => 'Method of pre-etching glass substrate for reducing releasing time' [patent_app_type] => new [patent_app_number] => 10/794286 [patent_app_country] => US [patent_app_date] => 2004-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1604 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20040192047.pdf [firstpage_image] =>[orig_patent_app_number] => 10794286 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/794286
Method of pre-etching glass substrate for reducing releasing time Mar 2, 2004 Abandoned
Array ( [id] => 7050913 [patent_doc_number] => 20050186800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'Self-masking defect removing method' [patent_app_type] => utility [patent_app_number] => 10/787276 [patent_app_country] => US [patent_app_date] => 2004-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2609 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20050186800.pdf [firstpage_image] =>[orig_patent_app_number] => 10787276 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/787276
Self-masking defect removing method Feb 24, 2004 Issued
Array ( [id] => 7415325 [patent_doc_number] => 20040159953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Method for manufacturing a semiconductor device having self-aligned contacts' [patent_app_type] => new [patent_app_number] => 10/779752 [patent_app_country] => US [patent_app_date] => 2004-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7367 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20040159953.pdf [firstpage_image] =>[orig_patent_app_number] => 10779752 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/779752
Method of manufacturing a semiconductor device having self-aligned contacts Feb 17, 2004 Issued
Array ( [id] => 7235745 [patent_doc_number] => 20040157467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Method for fabricating semiconductor intergrated circuit device' [patent_app_type] => new [patent_app_number] => 10/774406 [patent_app_country] => US [patent_app_date] => 2004-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 18804 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20040157467.pdf [firstpage_image] =>[orig_patent_app_number] => 10774406 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/774406
Method for fabricating semiconductor integrated circuit device Feb 9, 2004 Issued
Array ( [id] => 7415248 [patent_doc_number] => 20040159944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same' [patent_app_type] => new [patent_app_number] => 10/776076 [patent_app_country] => US [patent_app_date] => 2004-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6337 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20040159944.pdf [firstpage_image] =>[orig_patent_app_number] => 10776076 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/776076
Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same Feb 9, 2004 Issued
Menu