Search

John D. Lee

Examiner (ID: 17114)

Most Active Art Unit
2501
Art Unit(s)
2874, 2606, 2507, 2501, 2504, 3621
Total Applications
2783
Issued Applications
2467
Pending Applications
118
Abandoned Applications
198

Applications

Application numberTitle of the applicationFiling DateStatus
10/773886 Method and apparatus for producing gallium arsenide and silicon composites and devices incorporating same Feb 5, 2004 Abandoned
Array ( [id] => 7005250 [patent_doc_number] => 20050170563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Method for end point detection of polysilicon chemical mechanical polishing in an anti-fuse memory device' [patent_app_type] => utility [patent_app_number] => 10/767276 [patent_app_country] => US [patent_app_date] => 2004-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4732 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20050170563.pdf [firstpage_image] =>[orig_patent_app_number] => 10767276 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/767276
Method for end point detection polysilicon chemical mechanical polishing in an anti-fuse memory device Jan 28, 2004 Issued
Array ( [id] => 7089206 [patent_doc_number] => 20050009319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Method of forming buried wiring in semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/765155 [patent_app_country] => US [patent_app_date] => 2004-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3449 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20050009319.pdf [firstpage_image] =>[orig_patent_app_number] => 10765155 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/765155
Method of forming buried wiring in semiconductor device Jan 27, 2004 Issued
Array ( [id] => 760929 [patent_doc_number] => 07012027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-14 [patent_title] => 'Zirconium oxide and hafnium oxide etching using halogen containing chemicals' [patent_app_type] => utility [patent_app_number] => 10/766596 [patent_app_country] => US [patent_app_date] => 2004-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 6662 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/012/07012027.pdf [firstpage_image] =>[orig_patent_app_number] => 10766596 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/766596
Zirconium oxide and hafnium oxide etching using halogen containing chemicals Jan 26, 2004 Issued
Array ( [id] => 7183417 [patent_doc_number] => 20050161791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-28 [patent_title] => 'Multiple die-spacer for an integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/763349 [patent_app_country] => US [patent_app_date] => 2004-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1745 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20050161791.pdf [firstpage_image] =>[orig_patent_app_number] => 10763349 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/763349
Multiple die-spacer for an integrated circuit Jan 22, 2004 Abandoned
Array ( [id] => 7048407 [patent_doc_number] => 20050184294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-25 [patent_title] => 'End functionalization of carbon nanotubes' [patent_app_type] => utility [patent_app_number] => 10/761575 [patent_app_country] => US [patent_app_date] => 2004-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2276 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20050184294.pdf [firstpage_image] =>[orig_patent_app_number] => 10761575 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/761575
End functionalization of carbon nanotubes Jan 20, 2004 Issued
Array ( [id] => 642694 [patent_doc_number] => 07122824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-17 [patent_title] => 'Sublithographic contact structure, in particular for a phase change memory cell, and fabrication process thereof' [patent_app_type] => utility [patent_app_number] => 10/756195 [patent_app_country] => US [patent_app_date] => 2004-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 3242 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/122/07122824.pdf [firstpage_image] =>[orig_patent_app_number] => 10756195 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/756195
Sublithographic contact structure, in particular for a phase change memory cell, and fabrication process thereof Jan 12, 2004 Issued
Array ( [id] => 533930 [patent_doc_number] => 07172915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-06 [patent_title] => 'Optical-interference type display panel and method for making the same' [patent_app_type] => utility [patent_app_number] => 10/752666 [patent_app_country] => US [patent_app_date] => 2004-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 45 [patent_no_of_words] => 2831 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/172/07172915.pdf [firstpage_image] =>[orig_patent_app_number] => 10752666 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/752666
Optical-interference type display panel and method for making the same Jan 7, 2004 Issued
Array ( [id] => 7673241 [patent_doc_number] => 20040180538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Method for producing a copper connection' [patent_app_type] => new [patent_app_number] => 10/483046 [patent_app_country] => US [patent_app_date] => 2004-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1160 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20040180538.pdf [firstpage_image] =>[orig_patent_app_number] => 10483046 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/483046
Method for producing a copper connection Jan 6, 2004 Abandoned
Array ( [id] => 650896 [patent_doc_number] => 07112473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Double side stack packaging method' [patent_app_type] => utility [patent_app_number] => 10/747195 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1067 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/112/07112473.pdf [firstpage_image] =>[orig_patent_app_number] => 10747195 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/747195
Double side stack packaging method Dec 29, 2003 Issued
Array ( [id] => 7324172 [patent_doc_number] => 20040137675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Methods of manufacturing MOSFETS in semiconductor devices' [patent_app_type] => new [patent_app_number] => 10/745855 [patent_app_country] => US [patent_app_date] => 2003-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1150 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20040137675.pdf [firstpage_image] =>[orig_patent_app_number] => 10745855 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/745855
Methods of manufacturing MOSFETs in semiconductor devices Dec 25, 2003 Issued
Array ( [id] => 766329 [patent_doc_number] => 07008870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-07 [patent_title] => 'Structure applied to a photolithographic process and method for fabricating a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/707632 [patent_app_country] => US [patent_app_date] => 2003-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2346 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/008/07008870.pdf [firstpage_image] =>[orig_patent_app_number] => 10707632 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/707632
Structure applied to a photolithographic process and method for fabricating a semiconductor device Dec 25, 2003 Issued
Array ( [id] => 6996906 [patent_doc_number] => 20050136684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Gap-fill techniques' [patent_app_type] => utility [patent_app_number] => 10/746695 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6771 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20050136684.pdf [firstpage_image] =>[orig_patent_app_number] => 10746695 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/746695
Gap-fill techniques Dec 22, 2003 Abandoned
Array ( [id] => 363441 [patent_doc_number] => 07482252 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-01-27 [patent_title] => 'Method for reducing floating body effects in SOI semiconductor device without degrading mobility' [patent_app_type] => utility [patent_app_number] => 10/740546 [patent_app_country] => US [patent_app_date] => 2003-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2244 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/482/07482252.pdf [firstpage_image] =>[orig_patent_app_number] => 10740546 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/740546
Method for reducing floating body effects in SOI semiconductor device without degrading mobility Dec 21, 2003 Issued
Array ( [id] => 7097983 [patent_doc_number] => 20050130442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Method for fabricating transistor gate structures and gate dielectrics thereof' [patent_app_type] => utility [patent_app_number] => 10/734708 [patent_app_country] => US [patent_app_date] => 2003-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6401 [patent_no_of_claims] => 67 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20050130442.pdf [firstpage_image] =>[orig_patent_app_number] => 10734708 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/734708
Method for fabricating transistor gate structures and gate dielectrics thereof Dec 10, 2003 Issued
Array ( [id] => 7283640 [patent_doc_number] => 20040145031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment' [patent_app_type] => new [patent_app_number] => 10/726275 [patent_app_country] => US [patent_app_date] => 2003-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4822 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20040145031.pdf [firstpage_image] =>[orig_patent_app_number] => 10726275 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/726275
Semiconductor device, method for manufacturing the same, circuit substrate, electro-optical apparatus, and electronic equipment Dec 1, 2003 Issued
Array ( [id] => 7677494 [patent_doc_number] => 20040152332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Method for patterning dielectric layers on semiconductor substrates' [patent_app_type] => new [patent_app_number] => 10/724141 [patent_app_country] => US [patent_app_date] => 2003-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5229 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20040152332.pdf [firstpage_image] =>[orig_patent_app_number] => 10724141 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/724141
Method for patterning dielectric layers on semiconductor substrates Nov 30, 2003 Issued
Array ( [id] => 7144301 [patent_doc_number] => 20050118808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Method of reducing the pattern effect in the CMP process' [patent_app_type] => utility [patent_app_number] => 10/724201 [patent_app_country] => US [patent_app_date] => 2003-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4018 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20050118808.pdf [firstpage_image] =>[orig_patent_app_number] => 10724201 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/724201
Method of reducing the pattern effect in the CMP process Nov 30, 2003 Issued
Array ( [id] => 7677532 [patent_doc_number] => 20040152294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Method for forming metal line of semiconductor device' [patent_app_type] => new [patent_app_number] => 10/720976 [patent_app_country] => US [patent_app_date] => 2003-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2798 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20040152294.pdf [firstpage_image] =>[orig_patent_app_number] => 10720976 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/720976
Method for forming metal line of semiconductor device Nov 23, 2003 Abandoned
Array ( [id] => 7408713 [patent_doc_number] => 20040106244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-03 [patent_title] => 'Method of crystallizing amorphous silicon and device fabricated using the same' [patent_app_type] => new [patent_app_number] => 10/717676 [patent_app_country] => US [patent_app_date] => 2003-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3240 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20040106244.pdf [firstpage_image] =>[orig_patent_app_number] => 10717676 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/717676
Method of crystallizing amorphous silicon and device fabricated using the same Nov 20, 2003 Abandoned
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