Search

John D. Lee

Examiner (ID: 17114)

Most Active Art Unit
2501
Art Unit(s)
2874, 2606, 2507, 2501, 2504, 3621
Total Applications
2783
Issued Applications
2467
Pending Applications
118
Abandoned Applications
198

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1050088 [patent_doc_number] => 06861367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-01 [patent_title] => 'Semiconductor processing method using photoresist and an antireflective coating' [patent_app_type] => utility [patent_app_number] => 10/719640 [patent_app_country] => US [patent_app_date] => 2003-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2255 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/861/06861367.pdf [firstpage_image] =>[orig_patent_app_number] => 10719640 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/719640
Semiconductor processing method using photoresist and an antireflective coating Nov 20, 2003 Issued
Array ( [id] => 6939295 [patent_doc_number] => 20050112858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Contact hole forming method' [patent_app_type] => utility [patent_app_number] => 10/717582 [patent_app_country] => US [patent_app_date] => 2003-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1561 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20050112858.pdf [firstpage_image] =>[orig_patent_app_number] => 10717582 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/717582
Contact hole forming method Nov 20, 2003 Abandoned
Array ( [id] => 606818 [patent_doc_number] => 07154185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-26 [patent_title] => 'Encapsulation method for SBGA' [patent_app_type] => utility [patent_app_number] => 10/718191 [patent_app_country] => US [patent_app_date] => 2003-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 1130 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/154/07154185.pdf [firstpage_image] =>[orig_patent_app_number] => 10718191 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/718191
Encapsulation method for SBGA Nov 19, 2003 Issued
Array ( [id] => 482656 [patent_doc_number] => 07220654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Method for manufacturing semiconductor substrate' [patent_app_type] => utility [patent_app_number] => 10/716606 [patent_app_country] => US [patent_app_date] => 2003-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 38 [patent_no_of_words] => 4945 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/220/07220654.pdf [firstpage_image] =>[orig_patent_app_number] => 10716606 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/716606
Method for manufacturing semiconductor substrate Nov 19, 2003 Issued
Array ( [id] => 7324355 [patent_doc_number] => 20040137762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Annealing process and device of semiconductor wafer' [patent_app_type] => new [patent_app_number] => 10/716612 [patent_app_country] => US [patent_app_date] => 2003-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4721 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20040137762.pdf [firstpage_image] =>[orig_patent_app_number] => 10716612 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/716612
Annealing process and device of semiconductor wafer Nov 19, 2003 Issued
Array ( [id] => 7104155 [patent_doc_number] => 20050106881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Wafer reuse techniques' [patent_app_type] => utility [patent_app_number] => 10/718102 [patent_app_country] => US [patent_app_date] => 2003-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1109 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20050106881.pdf [firstpage_image] =>[orig_patent_app_number] => 10718102 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/718102
Wafer reuse techniques Nov 18, 2003 Issued
Array ( [id] => 749738 [patent_doc_number] => 07022602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'Nitrogen-enriched low-k barrier layer for a copper metallization layer' [patent_app_type] => utility [patent_app_number] => 10/716681 [patent_app_country] => US [patent_app_date] => 2003-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 6214 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/022/07022602.pdf [firstpage_image] =>[orig_patent_app_number] => 10716681 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/716681
Nitrogen-enriched low-k barrier layer for a copper metallization layer Nov 18, 2003 Issued
Array ( [id] => 7101337 [patent_doc_number] => 20050104063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Shallow trench isolation void detecting method and structure for the same' [patent_app_type] => utility [patent_app_number] => 10/714952 [patent_app_country] => US [patent_app_date] => 2003-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1131 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20050104063.pdf [firstpage_image] =>[orig_patent_app_number] => 10714952 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/714952
Shallow trench isolation void detecting method and structure for the same Nov 17, 2003 Issued
Array ( [id] => 744672 [patent_doc_number] => 07026207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-11 [patent_title] => 'Method of filling bit line contact via' [patent_app_type] => utility [patent_app_number] => 10/715611 [patent_app_country] => US [patent_app_date] => 2003-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 2082 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/026/07026207.pdf [firstpage_image] =>[orig_patent_app_number] => 10715611 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/715611
Method of filling bit line contact via Nov 17, 2003 Issued
Array ( [id] => 7101434 [patent_doc_number] => 20050104160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Bipolar junction transistor with improved extrinsic base region and method of fabrication' [patent_app_type] => utility [patent_app_number] => 10/715971 [patent_app_country] => US [patent_app_date] => 2003-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2059 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20050104160.pdf [firstpage_image] =>[orig_patent_app_number] => 10715971 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/715971
Bipolar junction transistor with improved extrinsic base region and method of fabrication Nov 16, 2003 Issued
Array ( [id] => 7101388 [patent_doc_number] => 20050104114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Method for forming polysilicon local interconnects' [patent_app_type] => utility [patent_app_number] => 10/714752 [patent_app_country] => US [patent_app_date] => 2003-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7465 [patent_no_of_claims] => 87 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0104/20050104114.pdf [firstpage_image] =>[orig_patent_app_number] => 10714752 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/714752
Method for forming polysilicon local interconnects Nov 16, 2003 Issued
Array ( [id] => 509689 [patent_doc_number] => 07195975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-27 [patent_title] => 'Method of forming bit line contact via' [patent_app_type] => utility [patent_app_number] => 10/714001 [patent_app_country] => US [patent_app_date] => 2003-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 3114 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/195/07195975.pdf [firstpage_image] =>[orig_patent_app_number] => 10714001 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/714001
Method of forming bit line contact via Nov 13, 2003 Issued
Array ( [id] => 446187 [patent_doc_number] => 07253113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-07 [patent_title] => 'Methods for using a silylation technique to reduce cell pitch in semiconductor devices' [patent_app_type] => utility [patent_app_number] => 10/713762 [patent_app_country] => US [patent_app_date] => 2003-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4141 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/253/07253113.pdf [firstpage_image] =>[orig_patent_app_number] => 10713762 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/713762
Methods for using a silylation technique to reduce cell pitch in semiconductor devices Nov 12, 2003 Issued
Array ( [id] => 7459575 [patent_doc_number] => 20040094837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Semiconductor device and method of formation' [patent_app_type] => new [patent_app_number] => 10/703796 [patent_app_country] => US [patent_app_date] => 2003-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3673 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20040094837.pdf [firstpage_image] =>[orig_patent_app_number] => 10703796 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/703796
Semiconductor device and method of formation Nov 6, 2003 Abandoned
Array ( [id] => 668440 [patent_doc_number] => 07094681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-22 [patent_title] => 'Semiconductor device fabrication method' [patent_app_type] => utility [patent_app_number] => 10/701476 [patent_app_country] => US [patent_app_date] => 2003-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 14 [patent_no_of_words] => 4527 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/094/07094681.pdf [firstpage_image] =>[orig_patent_app_number] => 10701476 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/701476
Semiconductor device fabrication method Nov 5, 2003 Issued
Array ( [id] => 994010 [patent_doc_number] => 06917111 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-12 [patent_title] => 'Semiconductor device having cell plugs' [patent_app_type] => utility [patent_app_number] => 10/697305 [patent_app_country] => US [patent_app_date] => 2003-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2955 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/917/06917111.pdf [firstpage_image] =>[orig_patent_app_number] => 10697305 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/697305
Semiconductor device having cell plugs Oct 30, 2003 Issued
Array ( [id] => 7324247 [patent_doc_number] => 20040137723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Manufacturing method of semiconductor device' [patent_app_type] => new [patent_app_number] => 10/696581 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3625 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20040137723.pdf [firstpage_image] =>[orig_patent_app_number] => 10696581 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/696581
Manufacturing method of semiconductor device Oct 29, 2003 Issued
Array ( [id] => 956182 [patent_doc_number] => 06955932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-18 [patent_title] => 'Single and double-gate pseudo-FET devices for semiconductor materials evaluation' [patent_app_type] => utility [patent_app_number] => 10/696632 [patent_app_country] => US [patent_app_date] => 2003-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6158 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/955/06955932.pdf [firstpage_image] =>[orig_patent_app_number] => 10696632 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/696632
Single and double-gate pseudo-FET devices for semiconductor materials evaluation Oct 28, 2003 Issued
Array ( [id] => 7465159 [patent_doc_number] => 20040166596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-26 [patent_title] => 'Manufacturing method of semiconductor device' [patent_app_type] => new [patent_app_number] => 10/695642 [patent_app_country] => US [patent_app_date] => 2003-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 23884 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20040166596.pdf [firstpage_image] =>[orig_patent_app_number] => 10695642 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/695642
Manufacturing method of semiconductor device Oct 28, 2003 Issued
Array ( [id] => 982258 [patent_doc_number] => 06927102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-09 [patent_title] => 'Semiconductor device and method of forming a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/694736 [patent_app_country] => US [patent_app_date] => 2003-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 86 [patent_no_of_words] => 14641 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/927/06927102.pdf [firstpage_image] =>[orig_patent_app_number] => 10694736 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/694736
Semiconductor device and method of forming a semiconductor device Oct 28, 2003 Issued
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