
John D. Lee
Examiner (ID: 17114)
| Most Active Art Unit | 2501 |
| Art Unit(s) | 2874, 2606, 2507, 2501, 2504, 3621 |
| Total Applications | 2783 |
| Issued Applications | 2467 |
| Pending Applications | 118 |
| Abandoned Applications | 198 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1050088
[patent_doc_number] => 06861367
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-03-01
[patent_title] => 'Semiconductor processing method using photoresist and an antireflective coating'
[patent_app_type] => utility
[patent_app_number] => 10/719640
[patent_app_country] => US
[patent_app_date] => 2003-11-21
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/861/06861367.pdf
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Array
(
[id] => 6939295
[patent_doc_number] => 20050112858
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[patent_kind] => A1
[patent_issue_date] => 2005-05-26
[patent_title] => 'Contact hole forming method'
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[patent_app_number] => 10/717582
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[patent_app_date] => 2003-11-21
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Array
(
[id] => 606818
[patent_doc_number] => 07154185
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[patent_kind] => B2
[patent_issue_date] => 2006-12-26
[patent_title] => 'Encapsulation method for SBGA'
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Array
(
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[patent_kind] => B2
[patent_issue_date] => 2007-05-22
[patent_title] => 'Method for manufacturing semiconductor substrate'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/716606 | Method for manufacturing semiconductor substrate | Nov 19, 2003 | Issued |
Array
(
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[patent_title] => 'Annealing process and device of semiconductor wafer'
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Array
(
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[patent_title] => 'Wafer reuse techniques'
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Array
(
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[patent_title] => 'Nitrogen-enriched low-k barrier layer for a copper metallization layer'
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[pdf_file] => patents/07/022/07022602.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/716681 | Nitrogen-enriched low-k barrier layer for a copper metallization layer | Nov 18, 2003 | Issued |
Array
(
[id] => 7101337
[patent_doc_number] => 20050104063
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[patent_issue_date] => 2005-05-19
[patent_title] => 'Shallow trench isolation void detecting method and structure for the same'
[patent_app_type] => utility
[patent_app_number] => 10/714952
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[patent_app_date] => 2003-11-18
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[firstpage_image] =>[orig_patent_app_number] => 10714952
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/714952 | Shallow trench isolation void detecting method and structure for the same | Nov 17, 2003 | Issued |
Array
(
[id] => 744672
[patent_doc_number] => 07026207
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-04-11
[patent_title] => 'Method of filling bit line contact via'
[patent_app_type] => utility
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[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/715611 | Method of filling bit line contact via | Nov 17, 2003 | Issued |
Array
(
[id] => 7101434
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[patent_issue_date] => 2005-05-19
[patent_title] => 'Bipolar junction transistor with improved extrinsic base region and method of fabrication'
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Array
(
[id] => 7101388
[patent_doc_number] => 20050104114
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[patent_title] => 'Method for forming polysilicon local interconnects'
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Array
(
[id] => 509689
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Array
(
[id] => 446187
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Array
(
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Array
(
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Array
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Array
(
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Array
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