Search

John D. Lee

Examiner (ID: 17114)

Most Active Art Unit
2501
Art Unit(s)
2874, 2606, 2507, 2501, 2504, 3621
Total Applications
2783
Issued Applications
2467
Pending Applications
118
Abandoned Applications
198

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5718445 [patent_doc_number] => 20060071218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-06 [patent_title] => 'Semiconductior multilayer structurehaving inhomogeneous quantum dots, light-emitting diode using same, semiconductor laser diode, semiconductor optical amplifier, and method for manufacturing them' [patent_app_type] => utility [patent_app_number] => 10/539635 [patent_app_country] => US [patent_app_date] => 2003-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 19995 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20060071218.pdf [firstpage_image] =>[orig_patent_app_number] => 10539635 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/539635
Semiconductior multilayer structurehaving inhomogeneous quantum dots, light-emitting diode using same, semiconductor laser diode, semiconductor optical amplifier, and method for manufacturing them Jun 12, 2003 Abandoned
10/111736 Method for thermally treating semiconductor substrates Jun 3, 2003 Abandoned
Array ( [id] => 6636454 [patent_doc_number] => 20030211721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-13 [patent_title] => 'Semiconductor device with a fluorinated silicate glass film as an interlayer metal dielectric film, and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 10/446876 [patent_app_country] => US [patent_app_date] => 2003-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7874 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20030211721.pdf [firstpage_image] =>[orig_patent_app_number] => 10446876 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/446876
Semiconductor device with a fluorinated silicate glass film as an interlayer metal dielectric film, and manufacturing method thereof May 28, 2003 Issued
Array ( [id] => 303960 [patent_doc_number] => 07535100 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-19 [patent_title] => 'Wafer bonding of thinned electronic materials and circuits to high performance substrates' [patent_app_type] => utility [patent_app_number] => 10/457692 [patent_app_country] => US [patent_app_date] => 2003-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 11086 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/535/07535100.pdf [firstpage_image] =>[orig_patent_app_number] => 10457692 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/457692
Wafer bonding of thinned electronic materials and circuits to high performance substrates May 19, 2003 Issued
Array ( [id] => 988423 [patent_doc_number] => 06921978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-26 [patent_title] => 'Method to generate porous organic dielectric' [patent_app_type] => utility [patent_app_number] => 10/249799 [patent_app_country] => US [patent_app_date] => 2003-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1922 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/921/06921978.pdf [firstpage_image] =>[orig_patent_app_number] => 10249799 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/249799
Method to generate porous organic dielectric May 7, 2003 Issued
Array ( [id] => 7434116 [patent_doc_number] => 20040065957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-08 [patent_title] => 'Semiconductor device having a low dielectric film and fabrication process thereof' [patent_app_type] => new [patent_app_number] => 10/258475 [patent_app_country] => US [patent_app_date] => 2003-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9305 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20040065957.pdf [firstpage_image] =>[orig_patent_app_number] => 10258475 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/258475
Semiconductor device having a low dielectric film and fabrication process thereof Apr 20, 2003 Abandoned
Array ( [id] => 634048 [patent_doc_number] => 07129104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-31 [patent_title] => 'Wavelength-insensitive radiation coupling for multi-quantum well sensor based on intersubband absorption' [patent_app_type] => utility [patent_app_number] => 10/409866 [patent_app_country] => US [patent_app_date] => 2003-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2208 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/129/07129104.pdf [firstpage_image] =>[orig_patent_app_number] => 10409866 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/409866
Wavelength-insensitive radiation coupling for multi-quantum well sensor based on intersubband absorption Apr 7, 2003 Issued
Array ( [id] => 6865281 [patent_doc_number] => 20030190807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-09 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => new [patent_app_number] => 10/408355 [patent_app_country] => US [patent_app_date] => 2003-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3122 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20030190807.pdf [firstpage_image] =>[orig_patent_app_number] => 10408355 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/408355
Method for manufacturing semiconductor device Apr 7, 2003 Abandoned
Array ( [id] => 6730308 [patent_doc_number] => 20030186498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Method for fabricating metal interconnection with reliability using ionized physical vapor deposition' [patent_app_type] => new [patent_app_number] => 10/396469 [patent_app_country] => US [patent_app_date] => 2003-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2135 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20030186498.pdf [firstpage_image] =>[orig_patent_app_number] => 10396469 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/396469
Method for fabricating metal interconnection with reliability using ionized physical vapor deposition Mar 25, 2003 Abandoned
Array ( [id] => 7406774 [patent_doc_number] => 20040175921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Reduction of the shear stress in copper via\'s in organic interlayer dielectric material' [patent_app_type] => new [patent_app_number] => 10/379346 [patent_app_country] => US [patent_app_date] => 2003-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3572 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20040175921.pdf [firstpage_image] =>[orig_patent_app_number] => 10379346 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/379346
Reduction of the shear stress in copper via's in organic interlayer dielectric material Mar 3, 2003 Issued
Array ( [id] => 1062812 [patent_doc_number] => 06849556 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-01 [patent_title] => 'Etching method, gate etching method, and method of manufacturing semiconductor devices' [patent_app_type] => utility [patent_app_number] => 10/364356 [patent_app_country] => US [patent_app_date] => 2003-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3455 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/849/06849556.pdf [firstpage_image] =>[orig_patent_app_number] => 10364356 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/364356
Etching method, gate etching method, and method of manufacturing semiconductor devices Feb 11, 2003 Issued
Array ( [id] => 7677531 [patent_doc_number] => 20040152295 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-05 [patent_title] => 'Sacrificial metal liner for copper' [patent_app_type] => new [patent_app_number] => 10/248636 [patent_app_country] => US [patent_app_date] => 2003-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3077 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20040152295.pdf [firstpage_image] =>[orig_patent_app_number] => 10248636 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/248636
Sacrificial metal liner for copper Feb 2, 2003 Abandoned
Array ( [id] => 1130591 [patent_doc_number] => 06787473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'Post-planarization clean-up' [patent_app_type] => B2 [patent_app_number] => 10/356095 [patent_app_country] => US [patent_app_date] => 2003-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3779 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/787/06787473.pdf [firstpage_image] =>[orig_patent_app_number] => 10356095 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/356095
Post-planarization clean-up Jan 30, 2003 Issued
Array ( [id] => 946590 [patent_doc_number] => 06964922 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-15 [patent_title] => 'Methods for forming metal interconnections for semiconductor devices having multiple metal depositions' [patent_app_type] => utility [patent_app_number] => 10/353386 [patent_app_country] => US [patent_app_date] => 2003-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6518 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/964/06964922.pdf [firstpage_image] =>[orig_patent_app_number] => 10353386 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/353386
Methods for forming metal interconnections for semiconductor devices having multiple metal depositions Jan 27, 2003 Issued
Array ( [id] => 1141163 [patent_doc_number] => 06781243 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-24 [patent_title] => 'Leadless leadframe package substitute and stack package' [patent_app_type] => B1 [patent_app_number] => 10/349695 [patent_app_country] => US [patent_app_date] => 2003-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5004 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/781/06781243.pdf [firstpage_image] =>[orig_patent_app_number] => 10349695 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/349695
Leadless leadframe package substitute and stack package Jan 21, 2003 Issued
Array ( [id] => 7629385 [patent_doc_number] => 06818971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-16 [patent_title] => 'Lead frame for resin-molded semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/347306 [patent_app_country] => US [patent_app_date] => 2003-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3489 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/818/06818971.pdf [firstpage_image] =>[orig_patent_app_number] => 10347306 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/347306
Lead frame for resin-molded semiconductor device Jan 20, 2003 Issued
Array ( [id] => 7324337 [patent_doc_number] => 20040137753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'METHOD FOR LOW TEMPERATURE LIQUID-PHASE DEPOSITION AND METHOD FOR CLEANING LIQUID-DEPOSITION APPARATUS' [patent_app_type] => new [patent_app_number] => 10/342245 [patent_app_country] => US [patent_app_date] => 2003-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2995 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20040137753.pdf [firstpage_image] =>[orig_patent_app_number] => 10342245 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/342245
Method for low temperature liquid-phase deposition and method for cleaning liquid-phase deposition apparatus Jan 14, 2003 Issued
Array ( [id] => 1136402 [patent_doc_number] => 06784497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'Semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/337280 [patent_app_country] => US [patent_app_date] => 2003-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1946 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/784/06784497.pdf [firstpage_image] =>[orig_patent_app_number] => 10337280 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/337280
Semiconductor device Jan 6, 2003 Issued
Array ( [id] => 6801271 [patent_doc_number] => 20030096436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Test structures and methods for inspection of semiconductor integrated circuits' [patent_app_type] => new [patent_app_number] => 10/338936 [patent_app_country] => US [patent_app_date] => 2003-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 23161 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20030096436.pdf [firstpage_image] =>[orig_patent_app_number] => 10338936 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/338936
Test structures and methods for inspection of semiconductor integrated circuits Jan 6, 2003 Issued
Array ( [id] => 5079705 [patent_doc_number] => 20070122929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-31 [patent_title] => 'Method and zone for sealing between two microstructure substrates' [patent_app_type] => utility [patent_app_number] => 10/500196 [patent_app_country] => US [patent_app_date] => 2002-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3859 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20070122929.pdf [firstpage_image] =>[orig_patent_app_number] => 10500196 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/500196
Method and zone for sealing between two microstructure substrates Dec 16, 2002 Issued
Menu