Search

John D. Lee

Examiner (ID: 17114)

Most Active Art Unit
2501
Art Unit(s)
2874, 2606, 2507, 2501, 2504, 3621
Total Applications
2783
Issued Applications
2467
Pending Applications
118
Abandoned Applications
198

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5790984 [patent_doc_number] => 20060012035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-19 [patent_title] => 'Method of packaging integrated circuits, and integrated circuit packages produced by the method' [patent_app_type] => utility [patent_app_number] => 10/538275 [patent_app_country] => US [patent_app_date] => 2002-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1885 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20060012035.pdf [firstpage_image] =>[orig_patent_app_number] => 10538275 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/538275
Method of packaging integrated circuits, and integrated circuit packages produced by the method Dec 9, 2002 Abandoned
Array ( [id] => 1062819 [patent_doc_number] => 06849563 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-01 [patent_title] => 'Method and apparatus for controlling coating thickness' [patent_app_type] => utility [patent_app_number] => 10/314798 [patent_app_country] => US [patent_app_date] => 2002-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4179 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/849/06849563.pdf [firstpage_image] =>[orig_patent_app_number] => 10314798 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/314798
Method and apparatus for controlling coating thickness Dec 8, 2002 Issued
Array ( [id] => 1080496 [patent_doc_number] => 06835654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-28 [patent_title] => 'Methods of forming an electrically conductive line' [patent_app_type] => B2 [patent_app_number] => 10/315429 [patent_app_country] => US [patent_app_date] => 2002-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 3884 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/835/06835654.pdf [firstpage_image] =>[orig_patent_app_number] => 10315429 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/315429
Methods of forming an electrically conductive line Dec 8, 2002 Issued
Array ( [id] => 1080455 [patent_doc_number] => 06835613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-28 [patent_title] => 'Method of producing an integrated circuit with a carbon nanotube' [patent_app_type] => B2 [patent_app_number] => 10/313886 [patent_app_country] => US [patent_app_date] => 2002-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2135 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/835/06835613.pdf [firstpage_image] =>[orig_patent_app_number] => 10313886 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/313886
Method of producing an integrated circuit with a carbon nanotube Dec 5, 2002 Issued
Array ( [id] => 6870161 [patent_doc_number] => 20030082850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-01 [patent_title] => 'Methods of fabricating semiconductor substrate-based BGA interconnections' [patent_app_type] => new [patent_app_number] => 10/310257 [patent_app_country] => US [patent_app_date] => 2002-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4538 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20030082850.pdf [firstpage_image] =>[orig_patent_app_number] => 10310257 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/310257
Methods of fabricating semiconductor substrate-based BGA interconnections Dec 3, 2002 Issued
Array ( [id] => 6758795 [patent_doc_number] => 20030122156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'Programmable resistance memory element and method for making same' [patent_app_type] => new [patent_app_number] => 10/308399 [patent_app_country] => US [patent_app_date] => 2002-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9345 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20030122156.pdf [firstpage_image] =>[orig_patent_app_number] => 10308399 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/308399
Programmable resistance memory element and method for making same Dec 1, 2002 Issued
Array ( [id] => 7466713 [patent_doc_number] => 20040101994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'Reducing line to line capacitance using oriented dielectric films' [patent_app_type] => new [patent_app_number] => 10/306066 [patent_app_country] => US [patent_app_date] => 2002-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1173 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20040101994.pdf [firstpage_image] =>[orig_patent_app_number] => 10306066 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/306066
Reducing line to line capacitance using oriented dielectric films Nov 26, 2002 Issued
Array ( [id] => 7450391 [patent_doc_number] => 20040067646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-08 [patent_title] => 'APPARATUS AND METHOD FOR FABRICATING ARRAYS OF ATOMIC-SCALE CONTACTS AND GAPS BETWEEN ELECTRODES AND APPLICATIONS THEREOF' [patent_app_type] => new [patent_app_number] => 10/305708 [patent_app_country] => US [patent_app_date] => 2002-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5546 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20040067646.pdf [firstpage_image] =>[orig_patent_app_number] => 10305708 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/305708
Apparatus and method for fabricating arrays of atomic-scale contacts and gaps between electrodes and applications thereof Nov 26, 2002 Issued
Array ( [id] => 790869 [patent_doc_number] => 06984893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-10 [patent_title] => 'Low temperature nitride used as Cu barrier layer' [patent_app_type] => utility [patent_app_number] => 10/303585 [patent_app_country] => US [patent_app_date] => 2002-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5049 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/984/06984893.pdf [firstpage_image] =>[orig_patent_app_number] => 10303585 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/303585
Low temperature nitride used as Cu barrier layer Nov 21, 2002 Issued
Array ( [id] => 6765784 [patent_doc_number] => 20030100184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'Method of forming a semiconductor device with a multi-layer WSix film with small grain size structure, and a semiconductor device having a polysilicon layer with a multi-layer WSix film formed thereon' [patent_app_type] => new [patent_app_number] => 10/301707 [patent_app_country] => US [patent_app_date] => 2002-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2427 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20030100184.pdf [firstpage_image] =>[orig_patent_app_number] => 10301707 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/301707
Method of forming a semiconductor device with a multi-layer WSix film with small grain size structure, and a semiconductor device having a polysilicon layer with a multi-layer WSix film formed thereon Nov 21, 2002 Abandoned
Array ( [id] => 7098092 [patent_doc_number] => 20050130551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Microstructures' [patent_app_type] => utility [patent_app_number] => 10/501516 [patent_app_country] => US [patent_app_date] => 2002-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5652 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20050130551.pdf [firstpage_image] =>[orig_patent_app_number] => 10501516 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/501516
Microstructures Nov 20, 2002 Issued
Array ( [id] => 1024600 [patent_doc_number] => 06884716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-26 [patent_title] => 'Method of forming a crystalline phase material' [patent_app_type] => utility [patent_app_number] => 10/300506 [patent_app_country] => US [patent_app_date] => 2002-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 3933 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/884/06884716.pdf [firstpage_image] =>[orig_patent_app_number] => 10300506 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/300506
Method of forming a crystalline phase material Nov 18, 2002 Issued
Array ( [id] => 7349106 [patent_doc_number] => 20040088855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Interposers for chip-scale packages, chip-scale packages including the interposers, test apparatus for effecting wafer-level testing of the chip-scale packages, and methods' [patent_app_type] => new [patent_app_number] => 10/292155 [patent_app_country] => US [patent_app_date] => 2002-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8645 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20040088855.pdf [firstpage_image] =>[orig_patent_app_number] => 10292155 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/292155
Interposers for chip-scale packages, chip-scale packages including the interposers, test apparatus for effecting wafer-level testing of the chip-scale packages, and methods Nov 10, 2002 Abandoned
Array ( [id] => 7625121 [patent_doc_number] => 06724049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-20 [patent_title] => 'SOI semiconductor device with insulating film having different properties relative to the buried insulating film' [patent_app_type] => B2 [patent_app_number] => 10/287508 [patent_app_country] => US [patent_app_date] => 2002-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 4713 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/724/06724049.pdf [firstpage_image] =>[orig_patent_app_number] => 10287508 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/287508
SOI semiconductor device with insulating film having different properties relative to the buried insulating film Nov 4, 2002 Issued
Array ( [id] => 1209261 [patent_doc_number] => 06713337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-30 [patent_title] => 'Method for manufacturing a semiconductor device having self-aligned contacts' [patent_app_type] => B2 [patent_app_number] => 10/259351 [patent_app_country] => US [patent_app_date] => 2002-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 29 [patent_no_of_words] => 7323 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/713/06713337.pdf [firstpage_image] =>[orig_patent_app_number] => 10259351 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/259351
Method for manufacturing a semiconductor device having self-aligned contacts Sep 29, 2002 Issued
Array ( [id] => 754419 [patent_doc_number] => 07018937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-28 [patent_title] => 'Compositions for removal of processing byproducts and method for using same' [patent_app_type] => utility [patent_app_number] => 10/231416 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 4279 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/018/07018937.pdf [firstpage_image] =>[orig_patent_app_number] => 10231416 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/231416
Compositions for removal of processing byproducts and method for using same Aug 28, 2002 Issued
Array ( [id] => 6692752 [patent_doc_number] => 20030040184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-27 [patent_title] => 'Method for fabricating a self-aligning mask' [patent_app_type] => new [patent_app_number] => 10/228886 [patent_app_country] => US [patent_app_date] => 2002-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3044 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20030040184.pdf [firstpage_image] =>[orig_patent_app_number] => 10228886 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/228886
Method for fabricating a self-aligning mask Aug 26, 2002 Issued
Array ( [id] => 6811807 [patent_doc_number] => 20030071357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Integrated circuitry' [patent_app_type] => new [patent_app_number] => 10/222305 [patent_app_country] => US [patent_app_date] => 2002-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2272 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0071/20030071357.pdf [firstpage_image] =>[orig_patent_app_number] => 10222305 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/222305
Integrated circuitry Aug 14, 2002 Issued
Array ( [id] => 6776659 [patent_doc_number] => 20030047739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-13 [patent_title] => 'Method to GaAs based lasers and a GaAs based laser' [patent_app_type] => new [patent_app_number] => 10/218497 [patent_app_country] => US [patent_app_date] => 2002-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10294 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20030047739.pdf [firstpage_image] =>[orig_patent_app_number] => 10218497 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/218497
Method to GaAs based lasers and a GaAs based laser Aug 14, 2002 Issued
Array ( [id] => 7634768 [patent_doc_number] => 06656850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-02 [patent_title] => 'Method for in-situ removal of side walls in MOM capacitor formation' [patent_app_type] => B2 [patent_app_number] => 10/215170 [patent_app_country] => US [patent_app_date] => 2002-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3885 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/656/06656850.pdf [firstpage_image] =>[orig_patent_app_number] => 10215170 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/215170
Method for in-situ removal of side walls in MOM capacitor formation Aug 7, 2002 Issued
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