
John D. Lee
Examiner (ID: 17114)
| Most Active Art Unit | 2501 |
| Art Unit(s) | 2874, 2606, 2507, 2501, 2504, 3621 |
| Total Applications | 2783 |
| Issued Applications | 2467 |
| Pending Applications | 118 |
| Abandoned Applications | 198 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5790984
[patent_doc_number] => 20060012035
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-19
[patent_title] => 'Method of packaging integrated circuits, and integrated circuit packages produced by the method'
[patent_app_type] => utility
[patent_app_number] => 10/538275
[patent_app_country] => US
[patent_app_date] => 2002-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 1885
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0012/20060012035.pdf
[firstpage_image] =>[orig_patent_app_number] => 10538275
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/538275 | Method of packaging integrated circuits, and integrated circuit packages produced by the method | Dec 9, 2002 | Abandoned |
Array
(
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[patent_doc_number] => 06849563
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-02-01
[patent_title] => 'Method and apparatus for controlling coating thickness'
[patent_app_type] => utility
[patent_app_number] => 10/314798
[patent_app_country] => US
[patent_app_date] => 2002-12-09
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/314798 | Method and apparatus for controlling coating thickness | Dec 8, 2002 | Issued |
Array
(
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[patent_doc_number] => 06835654
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[patent_kind] => B2
[patent_issue_date] => 2004-12-28
[patent_title] => 'Methods of forming an electrically conductive line'
[patent_app_type] => B2
[patent_app_number] => 10/315429
[patent_app_country] => US
[patent_app_date] => 2002-12-09
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/315429 | Methods of forming an electrically conductive line | Dec 8, 2002 | Issued |
Array
(
[id] => 1080455
[patent_doc_number] => 06835613
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-12-28
[patent_title] => 'Method of producing an integrated circuit with a carbon nanotube'
[patent_app_type] => B2
[patent_app_number] => 10/313886
[patent_app_country] => US
[patent_app_date] => 2002-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[firstpage_image] =>[orig_patent_app_number] => 10313886
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/313886 | Method of producing an integrated circuit with a carbon nanotube | Dec 5, 2002 | Issued |
Array
(
[id] => 6870161
[patent_doc_number] => 20030082850
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-05-01
[patent_title] => 'Methods of fabricating semiconductor substrate-based BGA interconnections'
[patent_app_type] => new
[patent_app_number] => 10/310257
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[patent_app_date] => 2002-12-04
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[pdf_file] => publications/A1/0082/20030082850.pdf
[firstpage_image] =>[orig_patent_app_number] => 10310257
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/310257 | Methods of fabricating semiconductor substrate-based BGA interconnections | Dec 3, 2002 | Issued |
Array
(
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[patent_issue_date] => 2003-07-03
[patent_title] => 'Programmable resistance memory element and method for making same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/308399 | Programmable resistance memory element and method for making same | Dec 1, 2002 | Issued |
Array
(
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[patent_title] => 'Reducing line to line capacitance using oriented dielectric films'
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[patent_app_date] => 2002-11-27
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[firstpage_image] =>[orig_patent_app_number] => 10306066
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/306066 | Reducing line to line capacitance using oriented dielectric films | Nov 26, 2002 | Issued |
Array
(
[id] => 7450391
[patent_doc_number] => 20040067646
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-08
[patent_title] => 'APPARATUS AND METHOD FOR FABRICATING ARRAYS OF ATOMIC-SCALE CONTACTS AND GAPS BETWEEN ELECTRODES AND APPLICATIONS THEREOF'
[patent_app_type] => new
[patent_app_number] => 10/305708
[patent_app_country] => US
[patent_app_date] => 2002-11-27
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[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 5546
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[pdf_file] => publications/A1/0067/20040067646.pdf
[firstpage_image] =>[orig_patent_app_number] => 10305708
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/305708 | Apparatus and method for fabricating arrays of atomic-scale contacts and gaps between electrodes and applications thereof | Nov 26, 2002 | Issued |
Array
(
[id] => 790869
[patent_doc_number] => 06984893
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-01-10
[patent_title] => 'Low temperature nitride used as Cu barrier layer'
[patent_app_type] => utility
[patent_app_number] => 10/303585
[patent_app_country] => US
[patent_app_date] => 2002-11-22
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/303585 | Low temperature nitride used as Cu barrier layer | Nov 21, 2002 | Issued |
Array
(
[id] => 6765784
[patent_doc_number] => 20030100184
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[patent_issue_date] => 2003-05-29
[patent_title] => 'Method of forming a semiconductor device with a multi-layer WSix film with small grain size structure, and a semiconductor device having a polysilicon layer with a multi-layer WSix film formed thereon'
[patent_app_type] => new
[patent_app_number] => 10/301707
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[pdf_file] => publications/A1/0100/20030100184.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/301707 | Method of forming a semiconductor device with a multi-layer WSix film with small grain size structure, and a semiconductor device having a polysilicon layer with a multi-layer WSix film formed thereon | Nov 21, 2002 | Abandoned |
Array
(
[id] => 7098092
[patent_doc_number] => 20050130551
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[patent_issue_date] => 2005-06-16
[patent_title] => 'Microstructures'
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[patent_app_number] => 10/501516
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Array
(
[id] => 1024600
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[patent_title] => 'Method of forming a crystalline phase material'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/300506 | Method of forming a crystalline phase material | Nov 18, 2002 | Issued |
Array
(
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[patent_title] => 'Interposers for chip-scale packages, chip-scale packages including the interposers, test apparatus for effecting wafer-level testing of the chip-scale packages, and methods'
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Array
(
[id] => 7625121
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[patent_issue_date] => 2004-04-20
[patent_title] => 'SOI semiconductor device with insulating film having different properties relative to the buried insulating film'
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Array
(
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[patent_title] => 'Method for manufacturing a semiconductor device having self-aligned contacts'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/259351 | Method for manufacturing a semiconductor device having self-aligned contacts | Sep 29, 2002 | Issued |
Array
(
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[patent_issue_date] => 2006-03-28
[patent_title] => 'Compositions for removal of processing byproducts and method for using same'
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Array
(
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Array
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Array
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[patent_title] => 'Method for in-situ removal of side walls in MOM capacitor formation'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/215170 | Method for in-situ removal of side walls in MOM capacitor formation | Aug 7, 2002 | Issued |