Search

John D. Lee

Examiner (ID: 17114)

Most Active Art Unit
2501
Art Unit(s)
2874, 2606, 2507, 2501, 2504, 3621
Total Applications
2783
Issued Applications
2467
Pending Applications
118
Abandoned Applications
198

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6408474 [patent_doc_number] => 20020182782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages' [patent_app_type] => new [patent_app_number] => 10/213597 [patent_app_country] => US [patent_app_date] => 2002-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10797 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20020182782.pdf [firstpage_image] =>[orig_patent_app_number] => 10213597 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/213597
Stereolithographic methods for fabricating hermetic semiconductor device packages and semiconductor devices including stereolithographically fabricated hermetic packages Aug 5, 2002 Abandoned
Array ( [id] => 1175530 [patent_doc_number] => 06746973 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-08 [patent_title] => 'Effect of substrate surface treatment on 193 NM resist processing' [patent_app_type] => B1 [patent_app_number] => 10/212985 [patent_app_country] => US [patent_app_date] => 2002-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7117 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/746/06746973.pdf [firstpage_image] =>[orig_patent_app_number] => 10212985 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/212985
Effect of substrate surface treatment on 193 NM resist processing Aug 4, 2002 Issued
Array ( [id] => 6785810 [patent_doc_number] => 20030137049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-24 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 10/208837 [patent_app_country] => US [patent_app_date] => 2002-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3026 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20030137049.pdf [firstpage_image] =>[orig_patent_app_number] => 10208837 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/208837
Semiconductor device with a low resistance wiring Jul 31, 2002 Issued
Array ( [id] => 6872798 [patent_doc_number] => 20030193095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-16 [patent_title] => 'Optical module equipped with a wiring plate' [patent_app_type] => new [patent_app_number] => 10/208167 [patent_app_country] => US [patent_app_date] => 2002-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5149 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20030193095.pdf [firstpage_image] =>[orig_patent_app_number] => 10208167 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/208167
Optical module equipped with a wiring plate Jul 28, 2002 Abandoned
Array ( [id] => 627378 [patent_doc_number] => 07135763 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-14 [patent_title] => 'Technique for attaching die to leads' [patent_app_type] => utility [patent_app_number] => 10/205940 [patent_app_country] => US [patent_app_date] => 2002-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4626 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/135/07135763.pdf [firstpage_image] =>[orig_patent_app_number] => 10205940 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/205940
Technique for attaching die to leads Jul 24, 2002 Issued
Array ( [id] => 1101589 [patent_doc_number] => 06815262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'Apparatus and method for attaching an integrated circuit sensor to a substrate' [patent_app_type] => B2 [patent_app_number] => 10/201087 [patent_app_country] => US [patent_app_date] => 2002-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1983 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/815/06815262.pdf [firstpage_image] =>[orig_patent_app_number] => 10201087 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/201087
Apparatus and method for attaching an integrated circuit sensor to a substrate Jul 21, 2002 Issued
Array ( [id] => 535940 [patent_doc_number] => 07180163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Support with integrated deposit of gas absorbing material for manufacturing microelectronic, microoptoelectronic or micromechanical devices' [patent_app_type] => utility [patent_app_number] => 10/211426 [patent_app_country] => US [patent_app_date] => 2002-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4140 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/180/07180163.pdf [firstpage_image] =>[orig_patent_app_number] => 10211426 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/211426
Support with integrated deposit of gas absorbing material for manufacturing microelectronic, microoptoelectronic or micromechanical devices Jul 18, 2002 Issued
Array ( [id] => 530603 [patent_doc_number] => 07183650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'Wiring glass substrate for connecting a semiconductor chip to a printed wiring substrate and a semiconductor module having the wiring glass substrate' [patent_app_type] => utility [patent_app_number] => 10/483175 [patent_app_country] => US [patent_app_date] => 2002-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 42 [patent_no_of_words] => 28863 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/183/07183650.pdf [firstpage_image] =>[orig_patent_app_number] => 10483175 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/483175
Wiring glass substrate for connecting a semiconductor chip to a printed wiring substrate and a semiconductor module having the wiring glass substrate Jul 11, 2002 Issued
Array ( [id] => 1256143 [patent_doc_number] => 06667231 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-23 [patent_title] => 'Method of forming barrier films for copper metallization over low dielectric constant insulators in an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 10/195006 [patent_app_country] => US [patent_app_date] => 2002-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5838 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/667/06667231.pdf [firstpage_image] =>[orig_patent_app_number] => 10195006 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/195006
Method of forming barrier films for copper metallization over low dielectric constant insulators in an integrated circuit Jul 11, 2002 Issued
Array ( [id] => 7406562 [patent_doc_number] => 20040175885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Method of manufacturing a semiconductor device comprising a non-volatile memory with memory cells' [patent_app_type] => new [patent_app_number] => 10/482185 [patent_app_country] => US [patent_app_date] => 2003-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4428 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20040175885.pdf [firstpage_image] =>[orig_patent_app_number] => 10482185 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/482185
Method of manufacturing a semiconductor device comprising a non-volatile memory with memory cells Jul 2, 2002 Issued
Array ( [id] => 521784 [patent_doc_number] => 07186640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'Silicon-rich oxide for copper damascene interconnect incorporating low dielectric constant dielectrics' [patent_app_type] => utility [patent_app_number] => 10/177855 [patent_app_country] => US [patent_app_date] => 2002-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2400 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/186/07186640.pdf [firstpage_image] =>[orig_patent_app_number] => 10177855 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/177855
Silicon-rich oxide for copper damascene interconnect incorporating low dielectric constant dielectrics Jun 19, 2002 Issued
Array ( [id] => 6170346 [patent_doc_number] => 20020153612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'Silicide pattern structures and methods of fabricating the same' [patent_app_type] => new [patent_app_number] => 10/173936 [patent_app_country] => US [patent_app_date] => 2002-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3953 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20020153612.pdf [firstpage_image] =>[orig_patent_app_number] => 10173936 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/173936
Silicide pattern structures and methods of fabricating the same Jun 16, 2002 Abandoned
Array ( [id] => 1205680 [patent_doc_number] => 06716745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-06 [patent_title] => 'Silicide pattern structures and methods of fabricating the same' [patent_app_type] => B2 [patent_app_number] => 10/174165 [patent_app_country] => US [patent_app_date] => 2002-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 32 [patent_no_of_words] => 3910 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/716/06716745.pdf [firstpage_image] =>[orig_patent_app_number] => 10174165 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/174165
Silicide pattern structures and methods of fabricating the same Jun 16, 2002 Issued
Array ( [id] => 1327319 [patent_doc_number] => 06599832 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-29 [patent_title] => 'Silicide pattern structures and methods of fabricating the same' [patent_app_type] => B2 [patent_app_number] => 10/174164 [patent_app_country] => US [patent_app_date] => 2002-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 32 [patent_no_of_words] => 3910 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/599/06599832.pdf [firstpage_image] =>[orig_patent_app_number] => 10174164 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/174164
Silicide pattern structures and methods of fabricating the same Jun 16, 2002 Issued
Array ( [id] => 1270189 [patent_doc_number] => 06653203 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Thin sidewall multi-step HDP deposition method to achieve completely filled high aspect ratio trenches' [patent_app_type] => B1 [patent_app_number] => 10/154285 [patent_app_country] => US [patent_app_date] => 2002-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3148 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/653/06653203.pdf [firstpage_image] =>[orig_patent_app_number] => 10154285 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/154285
Thin sidewall multi-step HDP deposition method to achieve completely filled high aspect ratio trenches May 22, 2002 Issued
Array ( [id] => 6540043 [patent_doc_number] => 20020137329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Method for fabricating a barrier layer' [patent_app_type] => new [patent_app_number] => 10/154219 [patent_app_country] => US [patent_app_date] => 2002-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1805 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20020137329.pdf [firstpage_image] =>[orig_patent_app_number] => 10154219 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/154219
Method for fabricating a barrier layer May 19, 2002 Abandoned
Array ( [id] => 6770086 [patent_doc_number] => 20030216026 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-20 [patent_title] => 'Method of forming dual damascene pattern using dual bottom anti-reflective coatings (BARC)' [patent_app_type] => new [patent_app_number] => 10/146276 [patent_app_country] => US [patent_app_date] => 2002-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2823 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20030216026.pdf [firstpage_image] =>[orig_patent_app_number] => 10146276 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/146276
Method of forming dual damascene pattern using dual bottom anti-reflective coatings (BARC) May 14, 2002 Issued
Array ( [id] => 1274032 [patent_doc_number] => 06649513 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Copper back-end-of-line by electropolish' [patent_app_type] => B1 [patent_app_number] => 10/146286 [patent_app_country] => US [patent_app_date] => 2002-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1216 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/649/06649513.pdf [firstpage_image] =>[orig_patent_app_number] => 10146286 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/146286
Copper back-end-of-line by electropolish May 14, 2002 Issued
Array ( [id] => 6435262 [patent_doc_number] => 20020127850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-12 [patent_title] => 'Integrated circuit with stop layer and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/144944 [patent_app_country] => US [patent_app_date] => 2002-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3295 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20020127850.pdf [firstpage_image] =>[orig_patent_app_number] => 10144944 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/144944
Integrated circuit with stop layer and method of manufacturing the same May 12, 2002 Abandoned
Array ( [id] => 1034474 [patent_doc_number] => 06875683 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-05 [patent_title] => 'Method of forming bump' [patent_app_type] => utility [patent_app_number] => 10/063576 [patent_app_country] => US [patent_app_date] => 2002-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 2922 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/875/06875683.pdf [firstpage_image] =>[orig_patent_app_number] => 10063576 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/063576
Method of forming bump May 2, 2002 Issued
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