Search

John D. Lee

Examiner (ID: 17114)

Most Active Art Unit
2501
Art Unit(s)
2874, 2606, 2507, 2501, 2504, 3621
Total Applications
2783
Issued Applications
2467
Pending Applications
118
Abandoned Applications
198

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1009377 [patent_doc_number] => 06900139 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-31 [patent_title] => 'Method for photoresist trim endpoint detection' [patent_app_type] => utility [patent_app_number] => 10/135175 [patent_app_country] => US [patent_app_date] => 2002-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5147 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/900/06900139.pdf [firstpage_image] =>[orig_patent_app_number] => 10135175 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/135175
Method for photoresist trim endpoint detection Apr 29, 2002 Issued
Array ( [id] => 6664288 [patent_doc_number] => 20030203614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-30 [patent_title] => 'METHOD FOR FORMING SILICON CONTAINING LAYERS ON A SUBSTRATE' [patent_app_type] => new [patent_app_number] => 10/136455 [patent_app_country] => US [patent_app_date] => 2002-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8244 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20030203614.pdf [firstpage_image] =>[orig_patent_app_number] => 10136455 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/136455
Method for forming silicon containing layers on a substrate Apr 28, 2002 Issued
Array ( [id] => 1014618 [patent_doc_number] => 06893960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-17 [patent_title] => 'Method for manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/123426 [patent_app_country] => US [patent_app_date] => 2002-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 36 [patent_no_of_words] => 6635 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/893/06893960.pdf [firstpage_image] =>[orig_patent_app_number] => 10123426 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/123426
Method for manufacturing a semiconductor device Apr 16, 2002 Issued
Array ( [id] => 1037486 [patent_doc_number] => 06872635 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-29 [patent_title] => 'Device transferring method, and device arraying method and image display unit fabricating method using the same' [patent_app_type] => utility [patent_app_number] => 10/297872 [patent_app_country] => US [patent_app_date] => 2002-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 39 [patent_no_of_words] => 23774 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/872/06872635.pdf [firstpage_image] =>[orig_patent_app_number] => 10297872 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/297872
Device transferring method, and device arraying method and image display unit fabricating method using the same Apr 8, 2002 Issued
Array ( [id] => 1180141 [patent_doc_number] => 06740598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-25 [patent_title] => 'Wiring layer dry etching method and semiconductor device manufacturing method' [patent_app_type] => B2 [patent_app_number] => 10/118375 [patent_app_country] => US [patent_app_date] => 2002-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3998 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/740/06740598.pdf [firstpage_image] =>[orig_patent_app_number] => 10118375 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/118375
Wiring layer dry etching method and semiconductor device manufacturing method Apr 8, 2002 Issued
Array ( [id] => 6730361 [patent_doc_number] => 20030186551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Integration scheme for metal gap fill with HDP and fixed abrasive CMP' [patent_app_type] => new [patent_app_number] => 10/108358 [patent_app_country] => US [patent_app_date] => 2002-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2204 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20030186551.pdf [firstpage_image] =>[orig_patent_app_number] => 10108358 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/108358
Integration scheme for metal gap fill with HDP and fixed abrasive CMP Mar 28, 2002 Abandoned
Array ( [id] => 1104683 [patent_doc_number] => 06812040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-02 [patent_title] => 'Method of fabricating a self-aligned via contact for a magnetic memory element' [patent_app_type] => B2 [patent_app_number] => 10/095816 [patent_app_country] => US [patent_app_date] => 2002-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2337 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812040.pdf [firstpage_image] =>[orig_patent_app_number] => 10095816 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/095816
Method of fabricating a self-aligned via contact for a magnetic memory element Mar 11, 2002 Issued
Array ( [id] => 6711229 [patent_doc_number] => 20030170978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-11 [patent_title] => 'Method of fabricating a dual damascene structure on a semiconductor substrate' [patent_app_type] => new [patent_app_number] => 10/087776 [patent_app_country] => US [patent_app_date] => 2002-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2213 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20030170978.pdf [firstpage_image] =>[orig_patent_app_number] => 10087776 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/087776
Method of fabricating a dual damascene structure on a semiconductor substrate Mar 4, 2002 Abandoned
Array ( [id] => 6081238 [patent_doc_number] => 20020081844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Method of manufacturing a barrier metal layer using atomic layer deposition' [patent_app_type] => new [patent_app_number] => 10/084193 [patent_app_country] => US [patent_app_date] => 2002-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5499 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20020081844.pdf [firstpage_image] =>[orig_patent_app_number] => 10084193 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/084193
Method of manufacturing a barrier metal layer using atomic layer deposition Feb 27, 2002 Abandoned
Array ( [id] => 6205449 [patent_doc_number] => 20020070456 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Semiconductor device having interconnection implemented by refractory metal nitride layer and refractory metal silicide layer and process of fabrication thereof' [patent_app_type] => new [patent_app_number] => 10/074936 [patent_app_country] => US [patent_app_date] => 2002-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4985 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20020070456.pdf [firstpage_image] =>[orig_patent_app_number] => 10074936 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/074936
Semiconductor device having interconnection implemented by refractory metal nitride layer and refractory metal silicide layer and process of fabrication thereof Feb 12, 2002 Issued
Array ( [id] => 6706456 [patent_doc_number] => 20030153190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Semiconductor processing method using photoresist and an antireflective coating' [patent_app_type] => new [patent_app_number] => 10/071425 [patent_app_country] => US [patent_app_date] => 2002-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2224 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20030153190.pdf [firstpage_image] =>[orig_patent_app_number] => 10071425 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/071425
Semiconductor processing method using photoresist and an antireflective coating Feb 7, 2002 Issued
Array ( [id] => 1297489 [patent_doc_number] => 06627529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-30 [patent_title] => 'Capacitance reduction by tunnel formation for use with semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/071906 [patent_app_country] => US [patent_app_date] => 2002-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3745 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/627/06627529.pdf [firstpage_image] =>[orig_patent_app_number] => 10071906 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/071906
Capacitance reduction by tunnel formation for use with semiconductor device Feb 6, 2002 Issued
Array ( [id] => 6209426 [patent_doc_number] => 20020072232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'Method of Forming an Electrically Conductive Line' [patent_app_type] => new [patent_app_number] => 10/061738 [patent_app_country] => US [patent_app_date] => 2002-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3866 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20020072232.pdf [firstpage_image] =>[orig_patent_app_number] => 10061738 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/061738
Methods of forming an electrically conductive line Jan 30, 2002 Issued
Array ( [id] => 1248282 [patent_doc_number] => 06673716 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Control of the deposition temperature to reduce the via and contact resistance of Ti and TiN deposited using ionized PVD techniques' [patent_app_type] => B1 [patent_app_number] => 10/060725 [patent_app_country] => US [patent_app_date] => 2002-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 9010 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/673/06673716.pdf [firstpage_image] =>[orig_patent_app_number] => 10060725 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/060725
Control of the deposition temperature to reduce the via and contact resistance of Ti and TiN deposited using ionized PVD techniques Jan 29, 2002 Issued
Array ( [id] => 1502408 [patent_doc_number] => 06486560 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Semiconductor device fabricated by a method of reducing electromigration in copper lines by forming an interim layer of calcium-doped copper seed layer in a chemical solution' [patent_app_type] => B1 [patent_app_number] => 10/041926 [patent_app_country] => US [patent_app_date] => 2002-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4756 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486560.pdf [firstpage_image] =>[orig_patent_app_number] => 10041926 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/041926
Semiconductor device fabricated by a method of reducing electromigration in copper lines by forming an interim layer of calcium-doped copper seed layer in a chemical solution Jan 6, 2002 Issued
Array ( [id] => 6539890 [patent_doc_number] => 20020137315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Method for depositing a tungsten silicide layer' [patent_app_type] => new [patent_app_number] => 10/039165 [patent_app_country] => US [patent_app_date] => 2002-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3383 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20020137315.pdf [firstpage_image] =>[orig_patent_app_number] => 10039165 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/039165
Method for depositing a tungsten silicide layer Jan 2, 2002 Issued
Array ( [id] => 5828771 [patent_doc_number] => 20020068431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Encapsulated metal structures for semiconductor devices and MIM capacitors including the same' [patent_app_type] => new [patent_app_number] => 10/034862 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2986 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20020068431.pdf [firstpage_image] =>[orig_patent_app_number] => 10034862 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/034862
Encapsulated metal structures for semiconductor devices and MIM capacitors including the same Dec 27, 2001 Issued
Array ( [id] => 6759855 [patent_doc_number] => 20030123216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'Deposition of tungsten for the formation of conformal tungsten silicide' [patent_app_type] => new [patent_app_number] => 10/033545 [patent_app_country] => US [patent_app_date] => 2001-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6537 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20030123216.pdf [firstpage_image] =>[orig_patent_app_number] => 10033545 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/033545
Deposition of tungsten for the formation of conformal tungsten silicide Dec 26, 2001 Abandoned
Array ( [id] => 6683437 [patent_doc_number] => 20030119301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'Method of fabricating an IMD layer to improve global planarization in subsequent CMP' [patent_app_type] => new [patent_app_number] => 10/022549 [patent_app_country] => US [patent_app_date] => 2001-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2385 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20030119301.pdf [firstpage_image] =>[orig_patent_app_number] => 10022549 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/022549
Method of fabricating an IMD layer to improve global planarization in subsequent CMP Dec 19, 2001 Abandoned
Array ( [id] => 5872199 [patent_doc_number] => 20020047970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Liquid crystal display' [patent_app_type] => new [patent_app_number] => 09/988676 [patent_app_country] => US [patent_app_date] => 2001-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5241 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20020047970.pdf [firstpage_image] =>[orig_patent_app_number] => 09988676 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/988676
Liquid crystal display Nov 19, 2001 Issued
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