Search

John D. Lee

Examiner (ID: 17114)

Most Active Art Unit
2501
Art Unit(s)
2874, 2606, 2507, 2501, 2504, 3621
Total Applications
2783
Issued Applications
2467
Pending Applications
118
Abandoned Applications
198

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6141847 [patent_doc_number] => 20020001949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'Low sheet resistance of titanium salicide process' [patent_app_type] => new [patent_app_number] => 09/920604 [patent_app_country] => US [patent_app_date] => 2001-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3500 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20020001949.pdf [firstpage_image] =>[orig_patent_app_number] => 09920604 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/920604
Low sheet resistance of titanium salicide process Aug 1, 2001 Issued
Array ( [id] => 534101 [patent_doc_number] => 07176079 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-13 [patent_title] => 'Method of fabricating a semiconductor device with a wet oxidation with steam process' [patent_app_type] => utility [patent_app_number] => 09/912558 [patent_app_country] => US [patent_app_date] => 2001-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3606 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/176/07176079.pdf [firstpage_image] =>[orig_patent_app_number] => 09912558 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/912558
Method of fabricating a semiconductor device with a wet oxidation with steam process Jul 25, 2001 Issued
Array ( [id] => 1495011 [patent_doc_number] => 06403461 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Method to reduce capacitance between metal lines' [patent_app_type] => B1 [patent_app_number] => 09/912606 [patent_app_country] => US [patent_app_date] => 2001-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2002 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/403/06403461.pdf [firstpage_image] =>[orig_patent_app_number] => 09912606 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/912606
Method to reduce capacitance between metal lines Jul 24, 2001 Issued
Array ( [id] => 6176813 [patent_doc_number] => 20020155704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'Method of forming a semiconductor device with an multilayer WSix film with small grain size' [patent_app_type] => new [patent_app_number] => 09/909816 [patent_app_country] => US [patent_app_date] => 2001-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2427 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20020155704.pdf [firstpage_image] =>[orig_patent_app_number] => 09909816 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/909816
Method of forming a semiconductor device with a multi-layer WSix film with small grain size structure Jul 22, 2001 Issued
Array ( [id] => 1235745 [patent_doc_number] => 06689680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-10 [patent_title] => 'Semiconductor device and method of formation' [patent_app_type] => B2 [patent_app_number] => 09/905756 [patent_app_country] => US [patent_app_date] => 2001-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3643 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/689/06689680.pdf [firstpage_image] =>[orig_patent_app_number] => 09905756 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/905756
Semiconductor device and method of formation Jul 13, 2001 Issued
Array ( [id] => 1458912 [patent_doc_number] => 06426297 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Differential pressure chemical-mechanical polishing in integrated circuit interconnects' [patent_app_type] => B1 [patent_app_number] => 09/905296 [patent_app_country] => US [patent_app_date] => 2001-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2925 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426297.pdf [firstpage_image] =>[orig_patent_app_number] => 09905296 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/905296
Differential pressure chemical-mechanical polishing in integrated circuit interconnects Jul 12, 2001 Issued
Array ( [id] => 7647020 [patent_doc_number] => 06476498 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Elimination of flux divergence in integrated circuit interconnects' [patent_app_type] => B1 [patent_app_number] => 09/905435 [patent_app_country] => US [patent_app_date] => 2001-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2980 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/476/06476498.pdf [firstpage_image] =>[orig_patent_app_number] => 09905435 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/905435
Elimination of flux divergence in integrated circuit interconnects Jul 12, 2001 Issued
Array ( [id] => 7400893 [patent_doc_number] => 20040023518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Method for manufacturing silicon wafer' [patent_app_type] => new [patent_app_number] => 10/332576 [patent_app_country] => US [patent_app_date] => 2003-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4092 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20040023518.pdf [firstpage_image] =>[orig_patent_app_number] => 10332576 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/332576
Method for manufacturing silicon wafer Jul 5, 2001 Issued
Array ( [id] => 6755933 [patent_doc_number] => 20030003710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Method of making a semiconductor device that includes a dual damascene interconnect' [patent_app_type] => new [patent_app_number] => 09/895676 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3324 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20030003710.pdf [firstpage_image] =>[orig_patent_app_number] => 09895676 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/895676
Method of making a semiconductor device that includes a dual damascene interconnect Jun 28, 2001 Abandoned
Array ( [id] => 1574807 [patent_doc_number] => 06468907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-22 [patent_title] => 'Method of manufacturing a copper wiring in a semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/880816 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2218 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/468/06468907.pdf [firstpage_image] =>[orig_patent_app_number] => 09880816 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/880816
Method of manufacturing a copper wiring in a semiconductor device Jun 14, 2001 Issued
Array ( [id] => 1231398 [patent_doc_number] => 06693028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-17 [patent_title] => 'Semiconductor device having multilayer wiring structure and method for manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 09/882435 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 5543 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/693/06693028.pdf [firstpage_image] =>[orig_patent_app_number] => 09882435 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/882435
Semiconductor device having multilayer wiring structure and method for manufacturing the same Jun 14, 2001 Issued
Array ( [id] => 1594596 [patent_doc_number] => 06383922 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Thermal stability improvement of CoSi2 film by stuffing in titanium' [patent_app_type] => B1 [patent_app_number] => 09/872558 [patent_app_country] => US [patent_app_date] => 2001-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 1721 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/383/06383922.pdf [firstpage_image] =>[orig_patent_app_number] => 09872558 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/872558
Thermal stability improvement of CoSi2 film by stuffing in titanium Jun 3, 2001 Issued
Array ( [id] => 7014594 [patent_doc_number] => 20010051432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-13 [patent_title] => 'Manufacturing method of semiconductor device' [patent_app_type] => new [patent_app_number] => 09/870085 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7826 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20010051432.pdf [firstpage_image] =>[orig_patent_app_number] => 09870085 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/870085
Manufacturing method of semiconductor device May 29, 2001 Issued
Array ( [id] => 6986884 [patent_doc_number] => 20010036716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Wire bonding to copper' [patent_app_type] => new [patent_app_number] => 09/864577 [patent_app_country] => US [patent_app_date] => 2001-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2136 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20010036716.pdf [firstpage_image] =>[orig_patent_app_number] => 09864577 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/864577
Wire bonding to copper May 23, 2001 Issued
Array ( [id] => 1565969 [patent_doc_number] => 06376354 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Wafer-level packaging process' [patent_app_type] => B1 [patent_app_number] => 09/854115 [patent_app_country] => US [patent_app_date] => 2001-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2102 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376354.pdf [firstpage_image] =>[orig_patent_app_number] => 09854115 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/854115
Wafer-level packaging process May 10, 2001 Issued
Array ( [id] => 1419432 [patent_doc_number] => 06506677 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Method of forming capped copper interconnects with reduced hillock formation and improved electromigration resistance' [patent_app_type] => B1 [patent_app_number] => 09/846186 [patent_app_country] => US [patent_app_date] => 2001-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4885 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/506/06506677.pdf [firstpage_image] =>[orig_patent_app_number] => 09846186 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/846186
Method of forming capped copper interconnects with reduced hillock formation and improved electromigration resistance May 1, 2001 Issued
Array ( [id] => 7093214 [patent_doc_number] => 20010034121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-25 [patent_title] => 'High selectivity Si-rich SiON etch-stop layer' [patent_app_type] => new [patent_app_number] => 09/838627 [patent_app_country] => US [patent_app_date] => 2001-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5955 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 379 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20010034121.pdf [firstpage_image] =>[orig_patent_app_number] => 09838627 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/838627
High selectivity Si-rich SiON etch-stop layer Apr 19, 2001 Issued
Array ( [id] => 7093216 [patent_doc_number] => 20010034123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-25 [patent_title] => 'Method of manufacturing a barrier metal layer using atomic layer deposition' [patent_app_type] => new [patent_app_number] => 09/826946 [patent_app_country] => US [patent_app_date] => 2001-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5497 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20010034123.pdf [firstpage_image] =>[orig_patent_app_number] => 09826946 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/826946
Method of manufacturing a barrier metal layer using atomic layer deposition Apr 5, 2001 Issued
Array ( [id] => 1261513 [patent_doc_number] => 06664180 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Method of forming smaller trench line width using a spacer hard mask' [patent_app_type] => B1 [patent_app_number] => 09/824415 [patent_app_country] => US [patent_app_date] => 2001-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2436 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/664/06664180.pdf [firstpage_image] =>[orig_patent_app_number] => 09824415 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/824415
Method of forming smaller trench line width using a spacer hard mask Apr 1, 2001 Issued
Array ( [id] => 7014576 [patent_doc_number] => 20010051422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-13 [patent_title] => 'Semiconductor devices and methods for manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/817935 [patent_app_country] => US [patent_app_date] => 2001-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5989 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20010051422.pdf [firstpage_image] =>[orig_patent_app_number] => 09817935 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/817935
Method for forming bonding pad structures in semiconductor devices Mar 26, 2001 Issued
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