
John D. Lee
Examiner (ID: 17114)
| Most Active Art Unit | 2501 |
| Art Unit(s) | 2874, 2606, 2507, 2501, 2504, 3621 |
| Total Applications | 2783 |
| Issued Applications | 2467 |
| Pending Applications | 118 |
| Abandoned Applications | 198 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1175442
[patent_doc_number] => 06746958
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-06-08
[patent_title] => 'Method of controlling the duration of an endpoint polishing process in a multistage polishing process'
[patent_app_type] => B1
[patent_app_number] => 09/817536
[patent_app_country] => US
[patent_app_date] => 2001-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 5067
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/746/06746958.pdf
[firstpage_image] =>[orig_patent_app_number] => 09817536
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/817536 | Method of controlling the duration of an endpoint polishing process in a multistage polishing process | Mar 25, 2001 | Issued |
Array
(
[id] => 1346635
[patent_doc_number] => 06583053
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-06-24
[patent_title] => 'Use of a sacrificial layer to facilitate metallization for small features'
[patent_app_type] => B2
[patent_app_number] => 09/816436
[patent_app_country] => US
[patent_app_date] => 2001-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 7
[patent_no_of_words] => 1645
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/583/06583053.pdf
[firstpage_image] =>[orig_patent_app_number] => 09816436
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/816436 | Use of a sacrificial layer to facilitate metallization for small features | Mar 22, 2001 | Issued |
Array
(
[id] => 1553591
[patent_doc_number] => 06348407
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-19
[patent_title] => 'Method to improve adhesion of organic dielectrics in dual damascene interconnects'
[patent_app_type] => B1
[patent_app_number] => 09/805955
[patent_app_country] => US
[patent_app_date] => 2001-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 2652
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/348/06348407.pdf
[firstpage_image] =>[orig_patent_app_number] => 09805955
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/805955 | Method to improve adhesion of organic dielectrics in dual damascene interconnects | Mar 14, 2001 | Issued |
Array
(
[id] => 6889419
[patent_doc_number] => 20010024874
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-09-27
[patent_title] => 'Manufacture of a semiconductor device'
[patent_app_type] => new
[patent_app_number] => 09/804788
[patent_app_country] => US
[patent_app_date] => 2001-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3389
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0024/20010024874.pdf
[firstpage_image] =>[orig_patent_app_number] => 09804788
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/804788 | Manufacture of a semiconductor device | Mar 12, 2001 | Issued |
Array
(
[id] => 7093210
[patent_doc_number] => 20010034118
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-10-25
[patent_title] => 'Method for defining windows with defferent etching depths simultaneously'
[patent_app_type] => new
[patent_app_number] => 09/803855
[patent_app_country] => US
[patent_app_date] => 2001-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2104
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0034/20010034118.pdf
[firstpage_image] =>[orig_patent_app_number] => 09803855
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/803855 | Method for defining windows with different etching depths simultaneously | Mar 11, 2001 | Issued |
Array
(
[id] => 6379135
[patent_doc_number] => 20020119656
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-08-29
[patent_title] => 'Methods of cleaning surfaces of copper-containing materials, and methods of forming openings to copper-containing substrates'
[patent_app_type] => new
[patent_app_number] => 09/797356
[patent_app_country] => US
[patent_app_date] => 2001-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3203
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 46
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0119/20020119656.pdf
[firstpage_image] =>[orig_patent_app_number] => 09797356
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/797356 | Methods of cleaning surfaces of copper-containing materials, and methods of forming openings to copper-containing substrates | Feb 27, 2001 | Issued |
Array
(
[id] => 1532580
[patent_doc_number] => 06410420
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-25
[patent_title] => 'Method of fabricating silicide pattern structures'
[patent_app_type] => B1
[patent_app_number] => 09/795882
[patent_app_country] => US
[patent_app_date] => 2001-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 32
[patent_no_of_words] => 3888
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/410/06410420.pdf
[firstpage_image] =>[orig_patent_app_number] => 09795882
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/795882 | Method of fabricating silicide pattern structures | Feb 27, 2001 | Issued |
Array
(
[id] => 1542765
[patent_doc_number] => 06372644
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-16
[patent_title] => 'Hydrogen passivated silicon nitride spacers for reduced nickel silicide bridging'
[patent_app_type] => B1
[patent_app_number] => 09/789765
[patent_app_country] => US
[patent_app_date] => 2001-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2448
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/372/06372644.pdf
[firstpage_image] =>[orig_patent_app_number] => 09789765
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/789765 | Hydrogen passivated silicon nitride spacers for reduced nickel silicide bridging | Feb 21, 2001 | Issued |
Array
(
[id] => 6908203
[patent_doc_number] => 20010010970
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-02
[patent_title] => 'DUAL - DAMASCENE DIELECTRIC STRUCTURES'
[patent_app_type] => new
[patent_app_number] => 09/788105
[patent_app_country] => US
[patent_app_date] => 2001-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4388
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 46
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0010/20010010970.pdf
[firstpage_image] =>[orig_patent_app_number] => 09788105
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/788105 | Dual-damascene dielectric structures | Feb 15, 2001 | Issued |
Array
(
[id] => 7093217
[patent_doc_number] => 20010034124
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-10-25
[patent_title] => 'Method and system for improving the dimensional accuracy of core source/drain marks'
[patent_app_type] => new
[patent_app_number] => 09/788186
[patent_app_country] => US
[patent_app_date] => 2001-02-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3284
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0034/20010034124.pdf
[firstpage_image] =>[orig_patent_app_number] => 09788186
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/788186 | Method and system for improving the dimensional accuracy of core source/drain marks | Feb 14, 2001 | Abandoned |
Array
(
[id] => 6896218
[patent_doc_number] => 20010027008
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-10-04
[patent_title] => 'Method for forming interconnect structure in semiconductor device'
[patent_app_type] => new
[patent_app_number] => 09/775605
[patent_app_country] => US
[patent_app_date] => 2001-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3804
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0027/20010027008.pdf
[firstpage_image] =>[orig_patent_app_number] => 09775605
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/775605 | Method for forming interconnect structure in semiconductor device | Feb 4, 2001 | Abandoned |
Array
(
[id] => 6961380
[patent_doc_number] => 20010012684
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-09
[patent_title] => 'Method of forming interconnect'
[patent_app_type] => new
[patent_app_number] => 09/753675
[patent_app_country] => US
[patent_app_date] => 2001-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7582
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0012/20010012684.pdf
[firstpage_image] =>[orig_patent_app_number] => 09753675
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/753675 | Method of forming interconnect | Jan 3, 2001 | Issued |
Array
(
[id] => 6630930
[patent_doc_number] => 20020086520
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-07-04
[patent_title] => 'Semiconductor device having bump electrode'
[patent_app_type] => new
[patent_app_number] => 09/750756
[patent_app_country] => US
[patent_app_date] => 2001-01-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2083
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0086/20020086520.pdf
[firstpage_image] =>[orig_patent_app_number] => 09750756
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/750756 | Semiconductor device having bump electrode | Jan 1, 2001 | Abandoned |
Array
(
[id] => 6111258
[patent_doc_number] => 20020173079
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-11-21
[patent_title] => 'Dual damascene integration scheme using a bilayer interlevel dielectric'
[patent_app_type] => new
[patent_app_number] => 09/751476
[patent_app_country] => US
[patent_app_date] => 2000-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2809
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0173/20020173079.pdf
[firstpage_image] =>[orig_patent_app_number] => 09751476
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/751476 | Dual damascene integration scheme using a bilayer interlevel dielectric | Dec 27, 2000 | Abandoned |
Array
(
[id] => 6130210
[patent_doc_number] => 20020076928
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-20
[patent_title] => 'Method for making a semiconductor device having copper conductive layers'
[patent_app_type] => new
[patent_app_number] => 09/741716
[patent_app_country] => US
[patent_app_date] => 2000-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1251
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0076/20020076928.pdf
[firstpage_image] =>[orig_patent_app_number] => 09741716
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/741716 | Method for making a semiconductor device having copper conductive layers | Dec 18, 2000 | Issued |
Array
(
[id] => 1585649
[patent_doc_number] => 06358848
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-19
[patent_title] => 'Method of reducing electromigration in copper lines by forming an interim layer of calcium-doped copper seed layer in a chemical solution and semiconductor device thereby formed'
[patent_app_type] => B1
[patent_app_number] => 09/728685
[patent_app_country] => US
[patent_app_date] => 2000-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 4656
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 339
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/358/06358848.pdf
[firstpage_image] =>[orig_patent_app_number] => 09728685
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/728685 | Method of reducing electromigration in copper lines by forming an interim layer of calcium-doped copper seed layer in a chemical solution and semiconductor device thereby formed | Nov 29, 2000 | Issued |
Array
(
[id] => 1306812
[patent_doc_number] => 06617248
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-09
[patent_title] => 'Method for forming a ruthenium metal layer'
[patent_app_type] => B1
[patent_app_number] => 09/710626
[patent_app_country] => US
[patent_app_date] => 2000-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 3229
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/617/06617248.pdf
[firstpage_image] =>[orig_patent_app_number] => 09710626
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/710626 | Method for forming a ruthenium metal layer | Nov 9, 2000 | Issued |
Array
(
[id] => 1336013
[patent_doc_number] => 06593183
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-15
[patent_title] => 'Semiconductor processing method using a barrier layer'
[patent_app_type] => B1
[patent_app_number] => 09/710546
[patent_app_country] => US
[patent_app_date] => 2000-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2669
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/593/06593183.pdf
[firstpage_image] =>[orig_patent_app_number] => 09710546
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/710546 | Semiconductor processing method using a barrier layer | Nov 7, 2000 | Issued |
Array
(
[id] => 1459531
[patent_doc_number] => 06391768
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-05-21
[patent_title] => 'Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structure'
[patent_app_type] => B1
[patent_app_number] => 09/703616
[patent_app_country] => US
[patent_app_date] => 2000-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 7
[patent_no_of_words] => 3709
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 434
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/391/06391768.pdf
[firstpage_image] =>[orig_patent_app_number] => 09703616
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/703616 | Process for CMP removal of excess trench or via filler metal which inhibits formation of concave regions on oxide surface of integrated circuit structure | Oct 29, 2000 | Issued |
Array
(
[id] => 1561212
[patent_doc_number] => 06362095
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-26
[patent_title] => 'Nickel silicide stripping after nickel silicide formation'
[patent_app_type] => B1
[patent_app_number] => 09/679876
[patent_app_country] => US
[patent_app_date] => 2000-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 20
[patent_no_of_words] => 4935
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/362/06362095.pdf
[firstpage_image] =>[orig_patent_app_number] => 09679876
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/679876 | Nickel silicide stripping after nickel silicide formation | Oct 4, 2000 | Issued |