Search

John D. Lee

Examiner (ID: 17114)

Most Active Art Unit
2501
Art Unit(s)
2874, 2606, 2507, 2501, 2504, 3621
Total Applications
2783
Issued Applications
2467
Pending Applications
118
Abandoned Applications
198

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1550426 [patent_doc_number] => 06399475 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Process for producing electrical connections on the surface of a semiconductor package with electrical-connection drops' [patent_app_type] => B1 [patent_app_number] => 09/679465 [patent_app_country] => US [patent_app_date] => 2000-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1597 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/399/06399475.pdf [firstpage_image] =>[orig_patent_app_number] => 09679465 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/679465
Process for producing electrical connections on the surface of a semiconductor package with electrical-connection drops Oct 3, 2000 Issued
Array ( [id] => 1165688 [patent_doc_number] => 06756315 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-29 [patent_title] => 'Method of forming contact openings' [patent_app_type] => B1 [patent_app_number] => 09/672836 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3743 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/756/06756315.pdf [firstpage_image] =>[orig_patent_app_number] => 09672836 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/672836
Method of forming contact openings Sep 28, 2000 Issued
Array ( [id] => 1416475 [patent_doc_number] => 06518178 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Method for forming a field effect transistor having increased breakdown voltage' [patent_app_type] => B1 [patent_app_number] => 09/675901 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 3776 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518178.pdf [firstpage_image] =>[orig_patent_app_number] => 09675901 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/675901
Method for forming a field effect transistor having increased breakdown voltage Sep 27, 2000 Issued
Array ( [id] => 1113010 [patent_doc_number] => 06803318 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-12 [patent_title] => 'Method of forming self aligned contacts' [patent_app_type] => B1 [patent_app_number] => 09/661666 [patent_app_country] => US [patent_app_date] => 2000-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 12619 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/803/06803318.pdf [firstpage_image] =>[orig_patent_app_number] => 09661666 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/661666
Method of forming self aligned contacts Sep 13, 2000 Issued
Array ( [id] => 1588965 [patent_doc_number] => 06482743 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Method of forming a semiconductor device using CMP to polish a metal film' [patent_app_type] => B1 [patent_app_number] => 09/660796 [patent_app_country] => US [patent_app_date] => 2000-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5341 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/482/06482743.pdf [firstpage_image] =>[orig_patent_app_number] => 09660796 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/660796
Method of forming a semiconductor device using CMP to polish a metal film Sep 12, 2000 Issued
Array ( [id] => 1446652 [patent_doc_number] => 06368963 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Passivation of semiconductor device surfaces using an iodine/ethanol solution' [patent_app_type] => B1 [patent_app_number] => 09/660396 [patent_app_country] => US [patent_app_date] => 2000-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2741 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/368/06368963.pdf [firstpage_image] =>[orig_patent_app_number] => 09660396 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/660396
Passivation of semiconductor device surfaces using an iodine/ethanol solution Sep 11, 2000 Issued
Array ( [id] => 1264533 [patent_doc_number] => 06660631 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Devices containing platinum-iridium films and methods of preparing such films and devices' [patent_app_type] => B1 [patent_app_number] => 09/652636 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10190 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/660/06660631.pdf [firstpage_image] =>[orig_patent_app_number] => 09652636 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/652636
Devices containing platinum-iridium films and methods of preparing such films and devices Aug 30, 2000 Issued
Array ( [id] => 1327244 [patent_doc_number] => 06599822 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Methods of fabricating semiconductor substrate-based BGA interconnection' [patent_app_type] => B1 [patent_app_number] => 09/649225 [patent_app_country] => US [patent_app_date] => 2000-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 32 [patent_no_of_words] => 4480 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/599/06599822.pdf [firstpage_image] =>[orig_patent_app_number] => 09649225 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/649225
Methods of fabricating semiconductor substrate-based BGA interconnection Aug 27, 2000 Issued
Array ( [id] => 1500398 [patent_doc_number] => 06486052 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Package having terminated plating layer and its manufacturing method' [patent_app_type] => B1 [patent_app_number] => 09/642806 [patent_app_country] => US [patent_app_date] => 2000-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 56 [patent_no_of_words] => 4130 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486052.pdf [firstpage_image] =>[orig_patent_app_number] => 09642806 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/642806
Package having terminated plating layer and its manufacturing method Aug 21, 2000 Issued
Array ( [id] => 1446628 [patent_doc_number] => 06368952 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Diffusion inhibited dielectric structure for diffusion enhanced conductor layer' [patent_app_type] => B1 [patent_app_number] => 09/638775 [patent_app_country] => US [patent_app_date] => 2000-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 5523 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/368/06368952.pdf [firstpage_image] =>[orig_patent_app_number] => 09638775 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/638775
Diffusion inhibited dielectric structure for diffusion enhanced conductor layer Aug 14, 2000 Issued
Array ( [id] => 1462634 [patent_doc_number] => 06350688 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Via RC improvement for copper damascene and beyond technology' [patent_app_type] => B1 [patent_app_number] => 09/629646 [patent_app_country] => US [patent_app_date] => 2000-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4962 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/350/06350688.pdf [firstpage_image] =>[orig_patent_app_number] => 09629646 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/629646
Via RC improvement for copper damascene and beyond technology Jul 31, 2000 Issued
Array ( [id] => 1570303 [patent_doc_number] => 06498098 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Method of forming embedded wiring in a groove in an insulating layer' [patent_app_type] => B1 [patent_app_number] => 09/625505 [patent_app_country] => US [patent_app_date] => 2000-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 37 [patent_no_of_words] => 6204 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/498/06498098.pdf [firstpage_image] =>[orig_patent_app_number] => 09625505 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/625505
Method of forming embedded wiring in a groove in an insulating layer Jul 25, 2000 Issued
Array ( [id] => 1520644 [patent_doc_number] => 06413811 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Method of forming a shared contact in a semiconductor device including MOSFETS' [patent_app_type] => B1 [patent_app_number] => 09/609926 [patent_app_country] => US [patent_app_date] => 2000-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4309 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/413/06413811.pdf [firstpage_image] =>[orig_patent_app_number] => 09609926 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/609926
Method of forming a shared contact in a semiconductor device including MOSFETS Jul 4, 2000 Issued
Array ( [id] => 1082926 [patent_doc_number] => 06833329 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-21 [patent_title] => 'Methods of forming oxide regions over semiconductor substrates' [patent_app_type] => B1 [patent_app_number] => 09/602395 [patent_app_country] => US [patent_app_date] => 2000-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3178 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/833/06833329.pdf [firstpage_image] =>[orig_patent_app_number] => 09602395 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/602395
Methods of forming oxide regions over semiconductor substrates Jun 21, 2000 Issued
Array ( [id] => 1566022 [patent_doc_number] => 06376365 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Method for fabricating semiconductor devices' [patent_app_type] => B1 [patent_app_number] => 09/598306 [patent_app_country] => US [patent_app_date] => 2000-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 30 [patent_no_of_words] => 6530 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376365.pdf [firstpage_image] =>[orig_patent_app_number] => 09598306 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/598306
Method for fabricating semiconductor devices Jun 20, 2000 Issued
Array ( [id] => 7631366 [patent_doc_number] => 06635566 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Method of making metallization and contact structures in an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/593967 [patent_app_country] => US [patent_app_date] => 2000-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 6784 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/635/06635566.pdf [firstpage_image] =>[orig_patent_app_number] => 09593967 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/593967
Method of making metallization and contact structures in an integrated circuit Jun 14, 2000 Issued
Array ( [id] => 1446630 [patent_doc_number] => 06368953 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Encapsulated metal structures for semiconductor devices and MIM capacitors including the same' [patent_app_type] => B1 [patent_app_number] => 09/567466 [patent_app_country] => US [patent_app_date] => 2000-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 2963 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/368/06368953.pdf [firstpage_image] =>[orig_patent_app_number] => 09567466 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/567466
Encapsulated metal structures for semiconductor devices and MIM capacitors including the same May 8, 2000 Issued
Array ( [id] => 1312266 [patent_doc_number] => 06610592 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-26 [patent_title] => 'Method for integrating low-K materials in semiconductor fabrication' [patent_app_type] => B1 [patent_app_number] => 09/557395 [patent_app_country] => US [patent_app_date] => 2000-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2398 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/610/06610592.pdf [firstpage_image] =>[orig_patent_app_number] => 09557395 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/557395
Method for integrating low-K materials in semiconductor fabrication Apr 23, 2000 Issued
Array ( [id] => 6081110 [patent_doc_number] => 20020081803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Method of fabricating dram capacitor' [patent_app_type] => new [patent_app_number] => 09/542715 [patent_app_country] => US [patent_app_date] => 2000-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2244 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20020081803.pdf [firstpage_image] =>[orig_patent_app_number] => 09542715 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/542715
Method of fabricating DRAM capacitor Apr 3, 2000 Issued
Array ( [id] => 4325226 [patent_doc_number] => 06329279 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Method of fabricating metal interconnect structure having outer air spacer' [patent_app_type] => 1 [patent_app_number] => 9/535495 [patent_app_country] => US [patent_app_date] => 2000-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1954 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329279.pdf [firstpage_image] =>[orig_patent_app_number] => 535495 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/535495
Method of fabricating metal interconnect structure having outer air spacer Mar 23, 2000 Issued
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