
John D. Lee
Examiner (ID: 17114)
| Most Active Art Unit | 2501 |
| Art Unit(s) | 2874, 2606, 2507, 2501, 2504, 3621 |
| Total Applications | 2783 |
| Issued Applications | 2467 |
| Pending Applications | 118 |
| Abandoned Applications | 198 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1462594
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[patent_title] => 'Chemical-mechanical polishing of semiconductors'
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[patent_app_number] => 09/534906
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Array
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[patent_issue_date] => 2001-08-07
[patent_title] => 'Method of fabricating interconnects'
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Array
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[patent_title] => 'Method for improved passive thermal flow in silicon on insulator devices'
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Array
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[patent_issue_date] => 2002-12-10
[patent_title] => 'Low temperature nitride used as Cu barrier layer'
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Array
(
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Array
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Array
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[patent_title] => 'Method for forming void-free metallization in an integrated circuit'
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Array
(
[id] => 1553619
[patent_doc_number] => 06348415
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[patent_issue_date] => 2002-02-19
[patent_title] => 'Planarization method for semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/472556
[patent_app_country] => US
[patent_app_date] => 1999-12-27
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/472556 | Planarization method for semiconductor device | Dec 26, 1999 | Issued |
| 09/367795 | METHOD FOR FABRICATING LOW-RESISTANCE CONTACTS ON NITRIDE SEMICONDUCTOR DEVICES | Dec 20, 1999 | Abandoned |
Array
(
[id] => 1466961
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[patent_title] => 'Method for in-situ removal of side walls in MOM capacitor formation'
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Array
(
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[patent_issue_date] => 2002-03-21
[patent_title] => 'PROCESS FOR FORMING A DUAL DAMASCENE BOND PAD STRUCTURE OVER ACTIVE CIRCUITRY'
[patent_app_type] => new
[patent_app_number] => 09/465075
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Array
(
[id] => 7014579
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[patent_title] => 'METHOD OF FORMING A CONTACT HOLE IN A SEMINCONDUCTOR DEVICE'
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Array
(
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Array
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Array
(
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Array
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Array
(
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Array
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Array
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Array
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