Search

John D. Lee

Examiner (ID: 17114)

Most Active Art Unit
2501
Art Unit(s)
2874, 2606, 2507, 2501, 2504, 3621
Total Applications
2783
Issued Applications
2467
Pending Applications
118
Abandoned Applications
198

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1462594 [patent_doc_number] => 06350678 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Chemical-mechanical polishing of semiconductors' [patent_app_type] => B1 [patent_app_number] => 09/534906 [patent_app_country] => US [patent_app_date] => 2000-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3618 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/350/06350678.pdf [firstpage_image] =>[orig_patent_app_number] => 09534906 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/534906
Chemical-mechanical polishing of semiconductors Mar 22, 2000 Issued
Array ( [id] => 4405104 [patent_doc_number] => 06271116 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Method of fabricating interconnects' [patent_app_type] => 1 [patent_app_number] => 9/528645 [patent_app_country] => US [patent_app_date] => 2000-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1815 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271116.pdf [firstpage_image] =>[orig_patent_app_number] => 528645 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/528645
Method of fabricating interconnects Mar 19, 2000 Issued
Array ( [id] => 1602630 [patent_doc_number] => 06432809 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method for improved passive thermal flow in silicon on insulator devices' [patent_app_type] => B1 [patent_app_number] => 09/514396 [patent_app_country] => US [patent_app_date] => 2000-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3946 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/432/06432809.pdf [firstpage_image] =>[orig_patent_app_number] => 09514396 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/514396
Method for improved passive thermal flow in silicon on insulator devices Feb 27, 2000 Issued
Array ( [id] => 1595739 [patent_doc_number] => 06492267 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Low temperature nitride used as Cu barrier layer' [patent_app_type] => B1 [patent_app_number] => 09/503105 [patent_app_country] => US [patent_app_date] => 2000-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5009 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492267.pdf [firstpage_image] =>[orig_patent_app_number] => 09503105 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/503105
Low temperature nitride used as Cu barrier layer Feb 10, 2000 Issued
Array ( [id] => 4270563 [patent_doc_number] => 06245675 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => '3D reservoir to improve electromigration resistance of tungsten plug' [patent_app_type] => 1 [patent_app_number] => 9/489966 [patent_app_country] => US [patent_app_date] => 2000-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1197 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/245/06245675.pdf [firstpage_image] =>[orig_patent_app_number] => 489966 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/489966
3D reservoir to improve electromigration resistance of tungsten plug Jan 23, 2000 Issued
Array ( [id] => 7640270 [patent_doc_number] => 06395644 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Process for fabricating a semiconductor device using a silicon-rich silicon nitride ARC' [patent_app_type] => B1 [patent_app_number] => 09/484606 [patent_app_country] => US [patent_app_date] => 2000-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3281 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/395/06395644.pdf [firstpage_image] =>[orig_patent_app_number] => 09484606 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/484606
Process for fabricating a semiconductor device using a silicon-rich silicon nitride ARC Jan 17, 2000 Issued
Array ( [id] => 1450095 [patent_doc_number] => 06455427 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Method for forming void-free metallization in an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/474865 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 11539 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/455/06455427.pdf [firstpage_image] =>[orig_patent_app_number] => 09474865 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/474865
Method for forming void-free metallization in an integrated circuit Dec 29, 1999 Issued
Array ( [id] => 1553619 [patent_doc_number] => 06348415 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Planarization method for semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/472556 [patent_app_country] => US [patent_app_date] => 1999-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1952 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348415.pdf [firstpage_image] =>[orig_patent_app_number] => 09472556 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/472556
Planarization method for semiconductor device Dec 26, 1999 Issued
09/367795 METHOD FOR FABRICATING LOW-RESISTANCE CONTACTS ON NITRIDE SEMICONDUCTOR DEVICES Dec 20, 1999 Abandoned
Array ( [id] => 1466961 [patent_doc_number] => 06458648 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Method for in-situ removal of side walls in MOM capacitor formation' [patent_app_type] => B1 [patent_app_number] => 09/466715 [patent_app_country] => US [patent_app_date] => 1999-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3845 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/458/06458648.pdf [firstpage_image] =>[orig_patent_app_number] => 09466715 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/466715
Method for in-situ removal of side walls in MOM capacitor formation Dec 16, 1999 Issued
Array ( [id] => 6342879 [patent_doc_number] => 20020034871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-21 [patent_title] => 'PROCESS FOR FORMING A DUAL DAMASCENE BOND PAD STRUCTURE OVER ACTIVE CIRCUITRY' [patent_app_type] => new [patent_app_number] => 09/465075 [patent_app_country] => US [patent_app_date] => 1999-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4977 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20020034871.pdf [firstpage_image] =>[orig_patent_app_number] => 09465075 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/465075
Process for forming a dual damascene bond pad structure over active circuitry Dec 15, 1999 Issued
Array ( [id] => 7014579 [patent_doc_number] => 20010051425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-13 [patent_title] => 'METHOD OF FORMING A CONTACT HOLE IN A SEMINCONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 09/453215 [patent_app_country] => US [patent_app_date] => 1999-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3732 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20010051425.pdf [firstpage_image] =>[orig_patent_app_number] => 09453215 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/453215
Method of forming a contact hole in a semiconductor device Dec 2, 1999 Issued
Array ( [id] => 4250656 [patent_doc_number] => 06207566 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Method for forming a metal plug on a semiconductor wafer' [patent_app_type] => 1 [patent_app_number] => 9/452105 [patent_app_country] => US [patent_app_date] => 1999-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 4040 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207566.pdf [firstpage_image] =>[orig_patent_app_number] => 452105 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/452105
Method for forming a metal plug on a semiconductor wafer Dec 1, 1999 Issued
Array ( [id] => 4302318 [patent_doc_number] => 06251761 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Process for polycrystalline silicon gates and high-K dielectric compatibility' [patent_app_type] => 1 [patent_app_number] => 9/447175 [patent_app_country] => US [patent_app_date] => 1999-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2350 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251761.pdf [firstpage_image] =>[orig_patent_app_number] => 447175 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/447175
Process for polycrystalline silicon gates and high-K dielectric compatibility Nov 21, 1999 Issued
Array ( [id] => 4287302 [patent_doc_number] => 06268293 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Method of forming wires on an integrated circuit chip' [patent_app_type] => 1 [patent_app_number] => 9/442956 [patent_app_country] => US [patent_app_date] => 1999-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2560 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268293.pdf [firstpage_image] =>[orig_patent_app_number] => 442956 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/442956
Method of forming wires on an integrated circuit chip Nov 17, 1999 Issued
Array ( [id] => 4156424 [patent_doc_number] => 06156656 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Process for manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/443006 [patent_app_country] => US [patent_app_date] => 1999-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2317 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/156/06156656.pdf [firstpage_image] =>[orig_patent_app_number] => 443006 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/443006
Process for manufacturing a semiconductor device Nov 17, 1999 Issued
Array ( [id] => 4303377 [patent_doc_number] => 06187693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Heat treatment of a tantalum oxide film' [patent_app_type] => 1 [patent_app_number] => 9/439346 [patent_app_country] => US [patent_app_date] => 1999-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 5938 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/187/06187693.pdf [firstpage_image] =>[orig_patent_app_number] => 439346 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/439346
Heat treatment of a tantalum oxide film Nov 14, 1999 Issued
Array ( [id] => 4420622 [patent_doc_number] => 06225217 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Method of manufacturing semiconductor device having multilayer wiring' [patent_app_type] => 1 [patent_app_number] => 9/439809 [patent_app_country] => US [patent_app_date] => 1999-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 53 [patent_no_of_words] => 6734 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225217.pdf [firstpage_image] =>[orig_patent_app_number] => 439809 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/439809
Method of manufacturing semiconductor device having multilayer wiring Nov 11, 1999 Issued
Array ( [id] => 4408365 [patent_doc_number] => 06265281 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Method for forming dielectric within a recess' [patent_app_type] => 1 [patent_app_number] => 9/432513 [patent_app_country] => US [patent_app_date] => 1999-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1889 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265281.pdf [firstpage_image] =>[orig_patent_app_number] => 432513 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/432513
Method for forming dielectric within a recess Nov 1, 1999 Issued
Array ( [id] => 4395518 [patent_doc_number] => 06297157 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Time ramped method for plating of high aspect ratio semiconductor vias and channels' [patent_app_type] => 1 [patent_app_number] => 9/431516 [patent_app_country] => US [patent_app_date] => 1999-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3585 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297157.pdf [firstpage_image] =>[orig_patent_app_number] => 431516 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/431516
Time ramped method for plating of high aspect ratio semiconductor vias and channels Oct 31, 1999 Issued
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