Search

John D. Lee

Examiner (ID: 17114)

Most Active Art Unit
2501
Art Unit(s)
2874, 2606, 2507, 2501, 2504, 3621
Total Applications
2783
Issued Applications
2467
Pending Applications
118
Abandoned Applications
198

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4292809 [patent_doc_number] => 06180518 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Method for forming vias in a low dielectric constant material' [patent_app_type] => 1 [patent_app_number] => 9/430226 [patent_app_country] => US [patent_app_date] => 1999-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3160 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/180/06180518.pdf [firstpage_image] =>[orig_patent_app_number] => 430226 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/430226
Method for forming vias in a low dielectric constant material Oct 28, 1999 Issued
Array ( [id] => 4154857 [patent_doc_number] => 06103619 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Method of forming a dual damascene structure on a semiconductor wafer' [patent_app_type] => 1 [patent_app_number] => 9/414895 [patent_app_country] => US [patent_app_date] => 1999-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3071 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 416 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/103/06103619.pdf [firstpage_image] =>[orig_patent_app_number] => 414895 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/414895
Method of forming a dual damascene structure on a semiconductor wafer Oct 7, 1999 Issued
Array ( [id] => 4246708 [patent_doc_number] => 06136709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Metal line deposition process' [patent_app_type] => 1 [patent_app_number] => 9/413265 [patent_app_country] => US [patent_app_date] => 1999-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2906 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/136/06136709.pdf [firstpage_image] =>[orig_patent_app_number] => 413265 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/413265
Metal line deposition process Oct 5, 1999 Issued
Array ( [id] => 4405882 [patent_doc_number] => 06232223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'High integrity borderless vias with protective sidewall spacer' [patent_app_type] => 1 [patent_app_number] => 9/406835 [patent_app_country] => US [patent_app_date] => 1999-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4730 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232223.pdf [firstpage_image] =>[orig_patent_app_number] => 406835 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/406835
High integrity borderless vias with protective sidewall spacer Sep 27, 1999 Issued
Array ( [id] => 4354181 [patent_doc_number] => 06218275 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Process for forming self-aligned contact of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/406556 [patent_app_country] => US [patent_app_date] => 1999-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 2395 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218275.pdf [firstpage_image] =>[orig_patent_app_number] => 406556 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/406556
Process for forming self-aligned contact of semiconductor device Sep 26, 1999 Issued
Array ( [id] => 4420602 [patent_doc_number] => 06225215 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Method for enhancing anti-reflective coatings used in photolithography of electronic devices' [patent_app_type] => 1 [patent_app_number] => 9/405805 [patent_app_country] => US [patent_app_date] => 1999-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 2804 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225215.pdf [firstpage_image] =>[orig_patent_app_number] => 405805 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/405805
Method for enhancing anti-reflective coatings used in photolithography of electronic devices Sep 23, 1999 Issued
Array ( [id] => 4286664 [patent_doc_number] => 06211066 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Electronic devices with barium barrier film and process for making same' [patent_app_type] => 1 [patent_app_number] => 9/399026 [patent_app_country] => US [patent_app_date] => 1999-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8244 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211066.pdf [firstpage_image] =>[orig_patent_app_number] => 399026 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/399026
Electronic devices with barium barrier film and process for making same Sep 21, 1999 Issued
Array ( [id] => 4117334 [patent_doc_number] => 06071823 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Deep trench bottle-shaped etch in centura mark II NG' [patent_app_type] => 1 [patent_app_number] => 9/399825 [patent_app_country] => US [patent_app_date] => 1999-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3266 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/071/06071823.pdf [firstpage_image] =>[orig_patent_app_number] => 399825 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/399825
Deep trench bottle-shaped etch in centura mark II NG Sep 20, 1999 Issued
Array ( [id] => 4408518 [patent_doc_number] => 06309962 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Film stack and etching sequence for dual damascene' [patent_app_type] => 1 [patent_app_number] => 9/396516 [patent_app_country] => US [patent_app_date] => 1999-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3156 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/309/06309962.pdf [firstpage_image] =>[orig_patent_app_number] => 396516 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/396516
Film stack and etching sequence for dual damascene Sep 14, 1999 Issued
Array ( [id] => 4406334 [patent_doc_number] => 06171956 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Method for improving the thermal conductivity of metal lines in integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/391496 [patent_app_country] => US [patent_app_date] => 1999-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1856 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/171/06171956.pdf [firstpage_image] =>[orig_patent_app_number] => 391496 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/391496
Method for improving the thermal conductivity of metal lines in integrated circuits Sep 7, 1999 Issued
Array ( [id] => 4233342 [patent_doc_number] => 06117765 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Method of preventing cracks in insulating spaces between metal wiring patterns' [patent_app_type] => 1 [patent_app_number] => 9/391616 [patent_app_country] => US [patent_app_date] => 1999-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2035 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/117/06117765.pdf [firstpage_image] =>[orig_patent_app_number] => 391616 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/391616
Method of preventing cracks in insulating spaces between metal wiring patterns Sep 6, 1999 Issued
Array ( [id] => 1467072 [patent_doc_number] => 06458703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-01 [patent_title] => 'Method for manufacturing semiconductor devices with allevration of thermal stress generation in conductive coating' [patent_app_type] => B2 [patent_app_number] => 09/389515 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 7301 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/458/06458703.pdf [firstpage_image] =>[orig_patent_app_number] => 09389515 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/389515
Method for manufacturing semiconductor devices with allevration of thermal stress generation in conductive coating Sep 2, 1999 Issued
Array ( [id] => 4329684 [patent_doc_number] => 06313042 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Cleaning contact with successive fluorine and hydrogen plasmas' [patent_app_type] => 1 [patent_app_number] => 9/390135 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4471 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/313/06313042.pdf [firstpage_image] =>[orig_patent_app_number] => 390135 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/390135
Cleaning contact with successive fluorine and hydrogen plasmas Sep 2, 1999 Issued
Array ( [id] => 4238490 [patent_doc_number] => 06080656 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Method for forming a self-aligned copper structure with improved planarity' [patent_app_type] => 1 [patent_app_number] => 9/387436 [patent_app_country] => US [patent_app_date] => 1999-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2036 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/080/06080656.pdf [firstpage_image] =>[orig_patent_app_number] => 387436 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/387436
Method for forming a self-aligned copper structure with improved planarity Aug 31, 1999 Issued
Array ( [id] => 4357096 [patent_doc_number] => 06174777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Method for fabricating a self aligned contact using a reverse self aligned contact etch' [patent_app_type] => 1 [patent_app_number] => 9/383596 [patent_app_country] => US [patent_app_date] => 1999-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1836 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/174/06174777.pdf [firstpage_image] =>[orig_patent_app_number] => 383596 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/383596
Method for fabricating a self aligned contact using a reverse self aligned contact etch Aug 25, 1999 Issued
Array ( [id] => 6224725 [patent_doc_number] => 20020004300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'ULTRA-THIN RESIST COATING QUALITYBY BY INCREASING SURFACE ROUGHNESS OF THE SUBSTRATE' [patent_app_type] => new [patent_app_number] => 09/371715 [patent_app_country] => US [patent_app_date] => 1999-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3856 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20020004300.pdf [firstpage_image] =>[orig_patent_app_number] => 09371715 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/371715
Ultra-thin resist coating quality by increasing surface roughness of the substrate Aug 8, 1999 Issued
Array ( [id] => 4247644 [patent_doc_number] => 06221770 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Low temperature plasma-enhanced formation of integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/364020 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 8140 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/221/06221770.pdf [firstpage_image] =>[orig_patent_app_number] => 364020 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/364020
Low temperature plasma-enhanced formation of integrated circuits Jul 29, 1999 Issued
Array ( [id] => 4405186 [patent_doc_number] => 06271122 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Method of compensating for material loss in a metal silicone layer in contacts of integrated circuit devices' [patent_app_type] => 1 [patent_app_number] => 9/351756 [patent_app_country] => US [patent_app_date] => 1999-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3242 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271122.pdf [firstpage_image] =>[orig_patent_app_number] => 351756 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/351756
Method of compensating for material loss in a metal silicone layer in contacts of integrated circuit devices Jul 11, 1999 Issued
Array ( [id] => 1469897 [patent_doc_number] => 06406995 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Pattern-sensitive deposition for damascene processing' [patent_app_type] => B1 [patent_app_number] => 09/345586 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3783 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/406/06406995.pdf [firstpage_image] =>[orig_patent_app_number] => 09345586 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/345586
Pattern-sensitive deposition for damascene processing Jun 29, 1999 Issued
Array ( [id] => 4381735 [patent_doc_number] => 06277742 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Method of protecting tungsten plug from corroding' [patent_app_type] => 1 [patent_app_number] => 9/342570 [patent_app_country] => US [patent_app_date] => 1999-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1478 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/277/06277742.pdf [firstpage_image] =>[orig_patent_app_number] => 342570 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/342570
Method of protecting tungsten plug from corroding Jun 28, 1999 Issued
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