Search

John D. Lee

Examiner (ID: 17114)

Most Active Art Unit
2501
Art Unit(s)
2874, 2606, 2507, 2501, 2504, 3621
Total Applications
2783
Issued Applications
2467
Pending Applications
118
Abandoned Applications
198

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4258900 [patent_doc_number] => 06204165 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Practical air dielectric interconnections by post-processing standard CMOS wafers' [patent_app_type] => 1 [patent_app_number] => 9/339705 [patent_app_country] => US [patent_app_date] => 1999-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 2888 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204165.pdf [firstpage_image] =>[orig_patent_app_number] => 339705 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/339705
Practical air dielectric interconnections by post-processing standard CMOS wafers Jun 23, 1999 Issued
Array ( [id] => 4155561 [patent_doc_number] => 06114234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Method of making a semiconductor with copper passivating film' [patent_app_type] => 1 [patent_app_number] => 9/338735 [patent_app_country] => US [patent_app_date] => 1999-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2661 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114234.pdf [firstpage_image] =>[orig_patent_app_number] => 338735 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/338735
Method of making a semiconductor with copper passivating film Jun 22, 1999 Issued
Array ( [id] => 1382299 [patent_doc_number] => 06551916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-22 [patent_title] => 'Bond-pad with pad edge strengthening structure' [patent_app_type] => B2 [patent_app_number] => 09/327875 [patent_app_country] => US [patent_app_date] => 1999-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5280 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/551/06551916.pdf [firstpage_image] =>[orig_patent_app_number] => 09327875 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/327875
Bond-pad with pad edge strengthening structure Jun 7, 1999 Issued
Array ( [id] => 4408841 [patent_doc_number] => 06300244 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 9/317955 [patent_app_country] => US [patent_app_date] => 1999-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9576 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300244.pdf [firstpage_image] =>[orig_patent_app_number] => 317955 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/317955
Semiconductor device and method of manufacturing the same May 24, 1999 Issued
Array ( [id] => 4369116 [patent_doc_number] => 06287946 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Fabrication of low resistance, non-alloyed, ohmic contacts to InP using non-stoichiometric InP layers' [patent_app_type] => 1 [patent_app_number] => 9/305896 [patent_app_country] => US [patent_app_date] => 1999-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3026 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287946.pdf [firstpage_image] =>[orig_patent_app_number] => 305896 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/305896
Fabrication of low resistance, non-alloyed, ohmic contacts to InP using non-stoichiometric InP layers May 4, 1999 Issued
Array ( [id] => 4369398 [patent_doc_number] => 06287966 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Low sheet resistance of titanium salicide process' [patent_app_type] => 1 [patent_app_number] => 9/303835 [patent_app_country] => US [patent_app_date] => 1999-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3483 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287966.pdf [firstpage_image] =>[orig_patent_app_number] => 303835 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/303835
Low sheet resistance of titanium salicide process May 2, 1999 Issued
Array ( [id] => 4420476 [patent_doc_number] => 06225203 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'PE-SiN spacer profile for C2 SAC isolation window' [patent_app_type] => 1 [patent_app_number] => 9/304334 [patent_app_country] => US [patent_app_date] => 1999-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2058 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225203.pdf [firstpage_image] =>[orig_patent_app_number] => 304334 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/304334
PE-SiN spacer profile for C2 SAC isolation window May 2, 1999 Issued
Array ( [id] => 1532597 [patent_doc_number] => 06410425 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Integrated circuit with stop layer and method of manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/292464 [patent_app_country] => US [patent_app_date] => 1999-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 18 [patent_no_of_words] => 3261 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/410/06410425.pdf [firstpage_image] =>[orig_patent_app_number] => 09292464 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/292464
Integrated circuit with stop layer and method of manufacturing the same Apr 14, 1999 Issued
Array ( [id] => 1523725 [patent_doc_number] => 06352913 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Damascene process for MOSFET fabrication' [patent_app_type] => B1 [patent_app_number] => 09/286185 [patent_app_country] => US [patent_app_date] => 1999-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1879 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/352/06352913.pdf [firstpage_image] =>[orig_patent_app_number] => 09286185 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/286185
Damascene process for MOSFET fabrication Apr 4, 1999 Issued
Array ( [id] => 1565021 [patent_doc_number] => 06339025 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-15 [patent_title] => 'Method of fabricating a copper capping layer' [patent_app_type] => B1 [patent_app_number] => 09/304436 [patent_app_country] => US [patent_app_date] => 1999-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1453 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/339/06339025.pdf [firstpage_image] =>[orig_patent_app_number] => 09304436 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/304436
Method of fabricating a copper capping layer Apr 2, 1999 Issued
Array ( [id] => 4378390 [patent_doc_number] => 06303491 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Method for fabricating self-aligned contact hole' [patent_app_type] => 1 [patent_app_number] => 9/283984 [patent_app_country] => US [patent_app_date] => 1999-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 1361 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303491.pdf [firstpage_image] =>[orig_patent_app_number] => 283984 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283984
Method for fabricating self-aligned contact hole Apr 1, 1999 Issued
09/270336 INTERCONNECTION SYSTEM AND METHOD FOR PRODUCING THE SAME Mar 15, 1999 Abandoned
Array ( [id] => 1327135 [patent_doc_number] => 06599811 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Semiconductor device having a shallow isolation trench' [patent_app_type] => B1 [patent_app_number] => 09/249556 [patent_app_country] => US [patent_app_date] => 1999-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 2926 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/599/06599811.pdf [firstpage_image] =>[orig_patent_app_number] => 09249556 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/249556
Semiconductor device having a shallow isolation trench Feb 11, 1999 Issued
Array ( [id] => 4287147 [patent_doc_number] => 06268283 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Method for forming dual damascene structure' [patent_app_type] => 1 [patent_app_number] => 9/248159 [patent_app_country] => US [patent_app_date] => 1999-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2150 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268283.pdf [firstpage_image] =>[orig_patent_app_number] => 248159 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/248159
Method for forming dual damascene structure Feb 8, 1999 Issued
Array ( [id] => 6858979 [patent_doc_number] => 20030089987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-15 [patent_title] => 'DUAL DAMASCENE MISALIGNMENT TOLERANT TECHNIQUES FOR VIAS AND SACRIFICIAL ETCH SEGMENTS' [patent_app_type] => new [patent_app_number] => 09/244788 [patent_app_country] => US [patent_app_date] => 1999-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10707 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20030089987.pdf [firstpage_image] =>[orig_patent_app_number] => 09244788 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/244788
DUAL DAMASCENE MISALIGNMENT TOLERANT TECHNIQUES FOR VIAS AND SACRIFICIAL ETCH SEGMENTS Feb 4, 1999 Abandoned
Array ( [id] => 4095296 [patent_doc_number] => 06096648 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Copper/low dielectric interconnect formation with reduced electromigration' [patent_app_type] => 1 [patent_app_number] => 9/237584 [patent_app_country] => US [patent_app_date] => 1999-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3709 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096648.pdf [firstpage_image] =>[orig_patent_app_number] => 237584 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/237584
Copper/low dielectric interconnect formation with reduced electromigration Jan 25, 1999 Issued
09/236406 WIRE BONDING TO COPPER Jan 22, 1999 Abandoned
Array ( [id] => 6000067 [patent_doc_number] => 20020028577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-07 [patent_title] => 'METHOD OF FORMING A REFRACTORY METAL SILICIDE' [patent_app_type] => new [patent_app_number] => 09/233377 [patent_app_country] => US [patent_app_date] => 1999-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3864 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20020028577.pdf [firstpage_image] =>[orig_patent_app_number] => 09233377 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/233377
Method of forming a refractory metal silicide Jan 17, 1999 Issued
Array ( [id] => 4290232 [patent_doc_number] => 06235628 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Method of forming dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide middle etch stop layer' [patent_app_type] => 1 [patent_app_number] => 9/225545 [patent_app_country] => US [patent_app_date] => 1999-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3874 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235628.pdf [firstpage_image] =>[orig_patent_app_number] => 225545 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225545
Method of forming dual damascene arrangement for metal interconnection with low k dielectric constant materials and oxide middle etch stop layer Jan 4, 1999 Issued
Array ( [id] => 4131829 [patent_doc_number] => 06147000 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Method for forming low dielectric passivation of copper interconnects' [patent_app_type] => 1 [patent_app_number] => 9/225546 [patent_app_country] => US [patent_app_date] => 1999-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4128 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147000.pdf [firstpage_image] =>[orig_patent_app_number] => 225546 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/225546
Method for forming low dielectric passivation of copper interconnects Jan 4, 1999 Issued
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