Search

John D. Lee

Examiner (ID: 17114)

Most Active Art Unit
2501
Art Unit(s)
2874, 2606, 2507, 2501, 2504, 3621
Total Applications
2783
Issued Applications
2467
Pending Applications
118
Abandoned Applications
198

Applications

Application numberTitle of the applicationFiling DateStatus
09/196330 FABRICATION METHOD OF DIFFUSION BARRIER LAYER OF A SEMICONDUCTOR DEVICE Nov 18, 1998 Abandoned
Array ( [id] => 4354681 [patent_doc_number] => 06200867 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Method for forming raised source and drain' [patent_app_type] => 1 [patent_app_number] => 9/192504 [patent_app_country] => US [patent_app_date] => 1998-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2499 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/200/06200867.pdf [firstpage_image] =>[orig_patent_app_number] => 192504 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/192504
Method for forming raised source and drain Nov 16, 1998 Issued
Array ( [id] => 4275919 [patent_doc_number] => 06281115 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Sidewall protection for a via hole formed in a photosensitive, low dielectric constant layer' [patent_app_type] => 1 [patent_app_number] => 9/192450 [patent_app_country] => US [patent_app_date] => 1998-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2384 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 384 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281115.pdf [firstpage_image] =>[orig_patent_app_number] => 192450 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/192450
Sidewall protection for a via hole formed in a photosensitive, low dielectric constant layer Nov 15, 1998 Issued
Array ( [id] => 4188637 [patent_doc_number] => 06153498 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Method of fabricating a buried contact' [patent_app_type] => 1 [patent_app_number] => 9/191247 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 1617 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153498.pdf [firstpage_image] =>[orig_patent_app_number] => 191247 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/191247
Method of fabricating a buried contact Nov 11, 1998 Issued
Array ( [id] => 4182521 [patent_doc_number] => 06150243 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Shallow junction formation by out-diffusion from a doped dielectric layer through a salicide layer' [patent_app_type] => 1 [patent_app_number] => 9/186065 [patent_app_country] => US [patent_app_date] => 1998-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 4498 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150243.pdf [firstpage_image] =>[orig_patent_app_number] => 186065 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/186065
Shallow junction formation by out-diffusion from a doped dielectric layer through a salicide layer Nov 4, 1998 Issued
Array ( [id] => 4155906 [patent_doc_number] => 06114258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Method of oxidizing a substrate in the presence of nitride and oxynitride films' [patent_app_type] => 1 [patent_app_number] => 9/175144 [patent_app_country] => US [patent_app_date] => 1998-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 10072 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114258.pdf [firstpage_image] =>[orig_patent_app_number] => 175144 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/175144
Method of oxidizing a substrate in the presence of nitride and oxynitride films Oct 18, 1998 Issued
Array ( [id] => 6961385 [patent_doc_number] => 20010012688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-09 [patent_title] => 'PROCESS FOR FORMING MINIATURE CONTACT HOLES IN SEMICONDUCTOR DEVICE WITHOUT SHORT-CIRCUIT' [patent_app_type] => new [patent_app_number] => 09/160100 [patent_app_country] => US [patent_app_date] => 1998-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4929 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20010012688.pdf [firstpage_image] =>[orig_patent_app_number] => 09160100 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/160100
PROCESS FOR FORMING MINIATURE CONTACT HOLES IN SEMICONDUCTOR DEVICE WITHOUT SHORT-CIRCUIT Sep 24, 1998 Abandoned
09/148096 METALLIC STRUCTURE HAVING ELECTROMIGRATION RESISTANCE AND MANUFACTURING METHOD THEREFOR Sep 3, 1998 Abandoned
Array ( [id] => 4344830 [patent_doc_number] => 06284655 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Method for producing low carbon/oxygen conductive layers' [patent_app_type] => 1 [patent_app_number] => 9/146297 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 7912 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/284/06284655.pdf [firstpage_image] =>[orig_patent_app_number] => 146297 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/146297
Method for producing low carbon/oxygen conductive layers Sep 2, 1998 Issued
Array ( [id] => 1450076 [patent_doc_number] => 06455420 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Method of forming a compound film of a semiconductor and a metal by self-alignment' [patent_app_type] => B1 [patent_app_number] => 09/136016 [patent_app_country] => US [patent_app_date] => 1998-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 4246 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/455/06455420.pdf [firstpage_image] =>[orig_patent_app_number] => 09136016 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/136016
Method of forming a compound film of a semiconductor and a metal by self-alignment Aug 18, 1998 Issued
09/132116 MONITORING BARRIER METAL DEPOSITION FOR METAL INTERCONNECT Aug 10, 1998 Abandoned
Array ( [id] => 4287329 [patent_doc_number] => 06268295 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/105008 [patent_app_country] => US [patent_app_date] => 1998-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 34 [patent_no_of_words] => 7146 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268295.pdf [firstpage_image] =>[orig_patent_app_number] => 105008 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/105008
Method of manufacturing semiconductor device Jun 25, 1998 Issued
Array ( [id] => 4169661 [patent_doc_number] => 06140225 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Method of manufacturing semiconductor device having multilayer wiring' [patent_app_type] => 1 [patent_app_number] => 9/104714 [patent_app_country] => US [patent_app_date] => 1998-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 53 [patent_no_of_words] => 6734 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140225.pdf [firstpage_image] =>[orig_patent_app_number] => 104714 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/104714
Method of manufacturing semiconductor device having multilayer wiring Jun 24, 1998 Issued
09/093945 METHOD OF FORMING A SILICON NITRIDE LAYER ON A SEMICONDUCTOR WAFER Jun 7, 1998 Abandoned
Array ( [id] => 1595774 [patent_doc_number] => 06492276 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Hard masking method for forming residue free oxygen containing plasma etched layer' [patent_app_type] => B1 [patent_app_number] => 09/086774 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 7260 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492276.pdf [firstpage_image] =>[orig_patent_app_number] => 09086774 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/086774
Hard masking method for forming residue free oxygen containing plasma etched layer May 28, 1998 Issued
Array ( [id] => 4085347 [patent_doc_number] => 06025279 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Method of reducing nitride and oxide peeling after planarization using an anneal' [patent_app_type] => 1 [patent_app_number] => 9/086824 [patent_app_country] => US [patent_app_date] => 1998-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2914 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025279.pdf [firstpage_image] =>[orig_patent_app_number] => 086824 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/086824
Method of reducing nitride and oxide peeling after planarization using an anneal May 28, 1998 Issued
Array ( [id] => 1418827 [patent_doc_number] => 06514884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-04 [patent_title] => 'Method for reforming base surface, method for manufacturing semiconductor device and equipment for manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 09/076744 [patent_app_country] => US [patent_app_date] => 1998-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 3798 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/514/06514884.pdf [firstpage_image] =>[orig_patent_app_number] => 09076744 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/076744
Method for reforming base surface, method for manufacturing semiconductor device and equipment for manufacturing the same May 12, 1998 Issued
Array ( [id] => 4381750 [patent_doc_number] => 06294466 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'HDP-CVD apparatus and process for depositing titanium films for semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/071514 [patent_app_country] => US [patent_app_date] => 1998-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7466 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294466.pdf [firstpage_image] =>[orig_patent_app_number] => 071514 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/071514
HDP-CVD apparatus and process for depositing titanium films for semiconductor devices Apr 30, 1998 Issued
Array ( [id] => 4234488 [patent_doc_number] => 06074962 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Method for the formation of silica-based coating film' [patent_app_type] => 1 [patent_app_number] => 9/070881 [patent_app_country] => US [patent_app_date] => 1998-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5130 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/074/06074962.pdf [firstpage_image] =>[orig_patent_app_number] => 070881 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/070881
Method for the formation of silica-based coating film Apr 30, 1998 Issued
Array ( [id] => 6877574 [patent_doc_number] => 20010003060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-07 [patent_title] => 'MULTILEVEL INTERCONNECTING STRUCTURE IN SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME' [patent_app_type] => new-utility [patent_app_number] => 09/066115 [patent_app_country] => US [patent_app_date] => 1998-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5545 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20010003060.pdf [firstpage_image] =>[orig_patent_app_number] => 09066115 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/066115
Multilevel interconnecting structure in semiconductor device and method of forming the same Apr 22, 1998 Issued
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