| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_title] => 'High throughput A1-Cu thin film sputtering process on small contact via for manufacturable beol wiring'
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Array
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[patent_issue_date] => 2000-01-18
[patent_title] => 'Method of fabricating semiconductor device with a gate-side air-gap structure'
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Array
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[patent_doc_number] => 05998254
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-07
[patent_title] => 'Method for creating a conductive connection between at least two zones of a first conductivity type'
[patent_app_type] => 1
[patent_app_number] => 9/055800
[patent_app_country] => US
[patent_app_date] => 1998-04-06
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Array
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[id] => 4381545
[patent_doc_number] => 06277729
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-08-21
[patent_title] => 'Method of manufacturing transistor barrier layer'
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[patent_app_number] => 9/042855
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[patent_app_date] => 1998-03-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/042855 | Method of manufacturing transistor barrier layer | Mar 16, 1998 | Issued |
Array
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[id] => 4409148
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[patent_issue_date] => 2001-05-08
[patent_title] => 'Process for forming metal interconnects with reduced or eliminated metal recess in vias'
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[patent_app_number] => 9/035735
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/035735 | Process for forming metal interconnects with reduced or eliminated metal recess in vias | Mar 4, 1998 | Issued |
Array
(
[id] => 4215727
[patent_doc_number] => 06087253
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[patent_kind] => NA
[patent_issue_date] => 2000-07-11
[patent_title] => 'Method of forming landing plugs for PMOS and NMOS'
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[patent_app_number] => 9/034541
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/034541 | Method of forming landing plugs for PMOS and NMOS | Mar 2, 1998 | Issued |
| 09/022596 | SEMICONDUCTOR INTEGRATED CIRCUIT HAVING MINIMIZED AREA CONTACTS AND METHOD THEREOF | Feb 11, 1998 | Abandoned |
Array
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[id] => 4258946
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[patent_issue_date] => 2001-03-20
[patent_title] => 'Damascene structure fabricated using a layer of silicon-based photoresist material'
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[firstpage_image] =>[orig_patent_app_number] => 017350
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Array
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[patent_doc_number] => 06228766
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[patent_kind] => NA
[patent_issue_date] => 2001-05-08
[patent_title] => 'Process for fabricating semiconductor device without separation between silicide layer and insulating layer'
[patent_app_type] => 1
[patent_app_number] => 9/010188
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[patent_app_date] => 1998-01-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/010188 | Process for fabricating semiconductor device without separation between silicide layer and insulating layer | Jan 20, 1998 | Issued |
Array
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[patent_issue_date] => 2001-09-18
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Array
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[patent_kind] => NA
[patent_issue_date] => 2001-04-17
[patent_title] => 'Silicide encapsulation of polysilicon gate and interconnect'
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Array
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Array
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Array
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Array
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