Search

John D. Lee

Examiner (ID: 17114)

Most Active Art Unit
2501
Art Unit(s)
2874, 2606, 2507, 2501, 2504, 3621
Total Applications
2783
Issued Applications
2467
Pending Applications
118
Abandoned Applications
198

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4169827 [patent_doc_number] => 06140236 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'High throughput A1-Cu thin film sputtering process on small contact via for manufacturable beol wiring' [patent_app_type] => 1 [patent_app_number] => 9/063094 [patent_app_country] => US [patent_app_date] => 1998-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2850 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140236.pdf [firstpage_image] =>[orig_patent_app_number] => 063094 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063094
High throughput A1-Cu thin film sputtering process on small contact via for manufacturable beol wiring Apr 20, 1998 Issued
Array ( [id] => 4136676 [patent_doc_number] => 06015746 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-18 [patent_title] => 'Method of fabricating semiconductor device with a gate-side air-gap structure' [patent_app_type] => 1 [patent_app_number] => 9/056530 [patent_app_country] => US [patent_app_date] => 1998-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2304 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/015/06015746.pdf [firstpage_image] =>[orig_patent_app_number] => 056530 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/056530
Method of fabricating semiconductor device with a gate-side air-gap structure Apr 6, 1998 Issued
Array ( [id] => 3944067 [patent_doc_number] => 05998254 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Method for creating a conductive connection between at least two zones of a first conductivity type' [patent_app_type] => 1 [patent_app_number] => 9/055800 [patent_app_country] => US [patent_app_date] => 1998-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2420 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998254.pdf [firstpage_image] =>[orig_patent_app_number] => 055800 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/055800
Method for creating a conductive connection between at least two zones of a first conductivity type Apr 5, 1998 Issued
Array ( [id] => 4381545 [patent_doc_number] => 06277729 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Method of manufacturing transistor barrier layer' [patent_app_type] => 1 [patent_app_number] => 9/042855 [patent_app_country] => US [patent_app_date] => 1998-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2260 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/277/06277729.pdf [firstpage_image] =>[orig_patent_app_number] => 042855 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/042855
Method of manufacturing transistor barrier layer Mar 16, 1998 Issued
Array ( [id] => 4409148 [patent_doc_number] => 06228757 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Process for forming metal interconnects with reduced or eliminated metal recess in vias' [patent_app_type] => 1 [patent_app_number] => 9/035735 [patent_app_country] => US [patent_app_date] => 1998-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4567 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/228/06228757.pdf [firstpage_image] =>[orig_patent_app_number] => 035735 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/035735
Process for forming metal interconnects with reduced or eliminated metal recess in vias Mar 4, 1998 Issued
Array ( [id] => 4215727 [patent_doc_number] => 06087253 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Method of forming landing plugs for PMOS and NMOS' [patent_app_type] => 1 [patent_app_number] => 9/034541 [patent_app_country] => US [patent_app_date] => 1998-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1776 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087253.pdf [firstpage_image] =>[orig_patent_app_number] => 034541 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/034541
Method of forming landing plugs for PMOS and NMOS Mar 2, 1998 Issued
09/022596 SEMICONDUCTOR INTEGRATED CIRCUIT HAVING MINIMIZED AREA CONTACTS AND METHOD THEREOF Feb 11, 1998 Abandoned
Array ( [id] => 4258946 [patent_doc_number] => 06204168 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Damascene structure fabricated using a layer of silicon-based photoresist material' [patent_app_type] => 1 [patent_app_number] => 9/017350 [patent_app_country] => US [patent_app_date] => 1998-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 28 [patent_no_of_words] => 6176 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204168.pdf [firstpage_image] =>[orig_patent_app_number] => 017350 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/017350
Damascene structure fabricated using a layer of silicon-based photoresist material Feb 1, 1998 Issued
Array ( [id] => 4409236 [patent_doc_number] => 06228766 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Process for fabricating semiconductor device without separation between silicide layer and insulating layer' [patent_app_type] => 1 [patent_app_number] => 9/010188 [patent_app_country] => US [patent_app_date] => 1998-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 5083 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/228/06228766.pdf [firstpage_image] =>[orig_patent_app_number] => 010188 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/010188
Process for fabricating semiconductor device without separation between silicide layer and insulating layer Jan 20, 1998 Issued
Array ( [id] => 4351022 [patent_doc_number] => 06291343 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Plasma annealing of substrates to improve adhesion' [patent_app_type] => 1 [patent_app_number] => 9/008796 [patent_app_country] => US [patent_app_date] => 1998-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5666 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291343.pdf [firstpage_image] =>[orig_patent_app_number] => 008796 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/008796
Plasma annealing of substrates to improve adhesion Jan 19, 1998 Issued
Array ( [id] => 4354196 [patent_doc_number] => 06218276 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Silicide encapsulation of polysilicon gate and interconnect' [patent_app_type] => 1 [patent_app_number] => 8/995875 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 12 [patent_no_of_words] => 3081 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218276.pdf [firstpage_image] =>[orig_patent_app_number] => 995875 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/995875
Silicide encapsulation of polysilicon gate and interconnect Dec 21, 1997 Issued
Array ( [id] => 4302524 [patent_doc_number] => 06187632 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Anneal technique for reducing amount of electronic trap in gate oxide film of transistor' [patent_app_type] => 1 [patent_app_number] => 8/994134 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 6860 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/187/06187632.pdf [firstpage_image] =>[orig_patent_app_number] => 994134 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/994134
Anneal technique for reducing amount of electronic trap in gate oxide film of transistor Dec 18, 1997 Issued
Array ( [id] => 4102522 [patent_doc_number] => 06100202 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Pre deposition stabilization method for forming a void free isotropically etched anisotropically patterned doped silicate glass layer' [patent_app_type] => 1 [patent_app_number] => 8/986530 [patent_app_country] => US [patent_app_date] => 1997-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 8425 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100202.pdf [firstpage_image] =>[orig_patent_app_number] => 986530 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/986530
Pre deposition stabilization method for forming a void free isotropically etched anisotropically patterned doped silicate glass layer Dec 7, 1997 Issued
Array ( [id] => 4294289 [patent_doc_number] => 06197689 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Semiconductor manufacture method with aluminum wiring layer patterning process' [patent_app_type] => 1 [patent_app_number] => 8/985482 [patent_app_country] => US [patent_app_date] => 1997-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 6710 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/197/06197689.pdf [firstpage_image] =>[orig_patent_app_number] => 985482 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/985482
Semiconductor manufacture method with aluminum wiring layer patterning process Dec 3, 1997 Issued
Array ( [id] => 4405780 [patent_doc_number] => 06232215 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Method for forming increased density for interconnection metallization' [patent_app_type] => 1 [patent_app_number] => 8/931235 [patent_app_country] => US [patent_app_date] => 1997-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3625 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232215.pdf [firstpage_image] =>[orig_patent_app_number] => 931235 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/931235
Method for forming increased density for interconnection metallization Sep 14, 1997 Issued
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