Application number | Title of the application | Filing Date | Status |
---|
08/309825 | DATA PROCESSING WITH SELF-TIMED FEATURE AND LOW POWER TRANSITION DETECTION | Sep 20, 1994 | Abandoned |
Array
(
[id] => 3594400
[patent_doc_number] => 05497106
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-05
[patent_title] => 'BICMOS output buffer circuit having overshoot protection'
[patent_app_type] => 1
[patent_app_number] => 8/308854
[patent_app_country] => US
[patent_app_date] => 1994-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2840
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/497/05497106.pdf
[firstpage_image] =>[orig_patent_app_number] => 308854
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/308854 | BICMOS output buffer circuit having overshoot protection | Sep 18, 1994 | Issued |
Array
(
[id] => 3512537
[patent_doc_number] => 05570044
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-29
[patent_title] => 'BiCMOS output driver with reduced static power consumption'
[patent_app_type] => 1
[patent_app_number] => 8/308470
[patent_app_country] => US
[patent_app_date] => 1994-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 3690
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/570/05570044.pdf
[firstpage_image] =>[orig_patent_app_number] => 308470
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/308470 | BiCMOS output driver with reduced static power consumption | Sep 18, 1994 | Issued |
Array
(
[id] => 3670064
[patent_doc_number] => 05668484
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-16
[patent_title] => 'High frequency clock signal distribution circuit with reduced clock skew'
[patent_app_type] => 1
[patent_app_number] => 8/306981
[patent_app_country] => US
[patent_app_date] => 1994-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 3074
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/668/05668484.pdf
[firstpage_image] =>[orig_patent_app_number] => 306981
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/306981 | High frequency clock signal distribution circuit with reduced clock skew | Sep 15, 1994 | Issued |
08/307983 | PROGRAMMABLE VOLTAGE STABILIZING CIRCUIT FOR A PROGRAMMABLE INTEGRATED CIRCUIT DEVICE | Sep 13, 1994 | Abandoned |
Array
(
[id] => 3557932
[patent_doc_number] => 05493235
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-20
[patent_title] => 'Programmable and stable threshold CMOS inverter'
[patent_app_type] => 1
[patent_app_number] => 8/305885
[patent_app_country] => US
[patent_app_date] => 1994-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 6150
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/493/05493235.pdf
[firstpage_image] =>[orig_patent_app_number] => 305885
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/305885 | Programmable and stable threshold CMOS inverter | Sep 13, 1994 | Issued |
Array
(
[id] => 3617786
[patent_doc_number] => 05565792
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-15
[patent_title] => 'Macrocell with product-term cascade and improved flip flop utilization'
[patent_app_type] => 1
[patent_app_number] => 8/301504
[patent_app_country] => US
[patent_app_date] => 1994-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 2931
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/565/05565792.pdf
[firstpage_image] =>[orig_patent_app_number] => 301504
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/301504 | Macrocell with product-term cascade and improved flip flop utilization | Sep 5, 1994 | Issued |
Array
(
[id] => 3596892
[patent_doc_number] => 05488319
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-30
[patent_title] => 'Latch interface for self-reset logic'
[patent_app_type] => 1
[patent_app_number] => 8/292673
[patent_app_country] => US
[patent_app_date] => 1994-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 3589
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/488/05488319.pdf
[firstpage_image] =>[orig_patent_app_number] => 292673
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/292673 | Latch interface for self-reset logic | Aug 17, 1994 | Issued |
Array
(
[id] => 3492681
[patent_doc_number] => 05475320
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-12
[patent_title] => 'Data processing with a self-timed approach to spurious transitions'
[patent_app_type] => 1
[patent_app_number] => 8/289073
[patent_app_country] => US
[patent_app_date] => 1994-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 17
[patent_no_of_words] => 3290
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/475/05475320.pdf
[firstpage_image] =>[orig_patent_app_number] => 289073
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/289073 | Data processing with a self-timed approach to spurious transitions | Aug 10, 1994 | Issued |
Array
(
[id] => 3467055
[patent_doc_number] => 05469080
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-21
[patent_title] => 'Low-power, logic signal level converter'
[patent_app_type] => 1
[patent_app_number] => 8/283272
[patent_app_country] => US
[patent_app_date] => 1994-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3031
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/469/05469080.pdf
[firstpage_image] =>[orig_patent_app_number] => 283272
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/283272 | Low-power, logic signal level converter | Jul 28, 1994 | Issued |
Array
(
[id] => 3613634
[patent_doc_number] => 05589783
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-31
[patent_title] => 'Variable input threshold adjustment'
[patent_app_type] => 1
[patent_app_number] => 8/282177
[patent_app_country] => US
[patent_app_date] => 1994-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 7
[patent_no_of_words] => 2444
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/589/05589783.pdf
[firstpage_image] =>[orig_patent_app_number] => 282177
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/282177 | Variable input threshold adjustment | Jul 28, 1994 | Issued |
08/282686 | HIGH SPEED DIFFERENTIAL LOGIC CIRCUIT | Jul 28, 1994 | Abandoned |
08/280382 | DIGITAL CIRCUIT TOPOLOGY OFFERING AN IMPROVED POWER DELAY PRODUCT | Jul 24, 1994 | Abandoned |
08/275185 | MULTI-FINGER INPUT BUFFER WITH TRANSISTOR GATES CAPACITIVELY COUPLED TO GROUND | Jul 13, 1994 | Abandoned |
Array
(
[id] => 3479602
[patent_doc_number] => 05428304
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-06-27
[patent_title] => 'Programmable gate array with special interconnects for adjacent gates and isolation devices used during programming'
[patent_app_type] => 1
[patent_app_number] => 8/272730
[patent_app_country] => US
[patent_app_date] => 1994-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2467
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 283
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/428/05428304.pdf
[firstpage_image] =>[orig_patent_app_number] => 272730
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/272730 | Programmable gate array with special interconnects for adjacent gates and isolation devices used during programming | Jul 7, 1994 | Issued |
Array
(
[id] => 3497686
[patent_doc_number] => 05537055
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-16
[patent_title] => 'Method for protecting an ASIC by resetting it after a predetermined time period'
[patent_app_type] => 1
[patent_app_number] => 8/269083
[patent_app_country] => US
[patent_app_date] => 1994-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2745
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/537/05537055.pdf
[firstpage_image] =>[orig_patent_app_number] => 269083
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/269083 | Method for protecting an ASIC by resetting it after a predetermined time period | Jun 29, 1994 | Issued |
Array
(
[id] => 3736593
[patent_doc_number] => 05635854
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-03
[patent_title] => 'Programmable logic integrated circuit including verify circuitry for classifying fuse link states as validly closed, validly open or invalid'
[patent_app_type] => 1
[patent_app_number] => 8/247934
[patent_app_country] => US
[patent_app_date] => 1994-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4415
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/635/05635854.pdf
[firstpage_image] =>[orig_patent_app_number] => 247934
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/247934 | Programmable logic integrated circuit including verify circuitry for classifying fuse link states as validly closed, validly open or invalid | May 23, 1994 | Issued |
Array
(
[id] => 3514721
[patent_doc_number] => 05587671
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-24
[patent_title] => 'Semiconductor device having an output buffer which reduces signal degradation due to leakage of current'
[patent_app_type] => 1
[patent_app_number] => 8/238972
[patent_app_country] => US
[patent_app_date] => 1994-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 4627
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/587/05587671.pdf
[firstpage_image] =>[orig_patent_app_number] => 238972
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/238972 | Semiconductor device having an output buffer which reduces signal degradation due to leakage of current | May 4, 1994 | Issued |
Array
(
[id] => 3495645
[patent_doc_number] => 05440249
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-08
[patent_title] => 'Voltage level translator circuit with cascoded output transistors'
[patent_app_type] => 1
[patent_app_number] => 8/237570
[patent_app_country] => US
[patent_app_date] => 1994-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3153
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/440/05440249.pdf
[firstpage_image] =>[orig_patent_app_number] => 237570
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/237570 | Voltage level translator circuit with cascoded output transistors | May 2, 1994 | Issued |
Array
(
[id] => 3430239
[patent_doc_number] => 05416368
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-16
[patent_title] => 'Level conversion output circuit with reduced power consumption'
[patent_app_type] => 1
[patent_app_number] => 8/232407
[patent_app_country] => US
[patent_app_date] => 1994-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 3759
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 495
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/416/05416368.pdf
[firstpage_image] =>[orig_patent_app_number] => 232407
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/232407 | Level conversion output circuit with reduced power consumption | Apr 24, 1994 | Issued |