John D Pak

Array ( [id] => 3464985 [patent_doc_number] => 05442307 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-15 [patent_title] => 'Interface circuit with backgate bias control of a transistor' [patent_app_type] => 1 [patent_app_number] => 8/226683 [patent_app_country] => US [patent_app_date] => 1994-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 10420 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/442/05442307.pdf [firstpage_image] =>[orig_patent_app_number] => 226683 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3458419 [patent_doc_number] => 05451890 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-19 [patent_title] => 'Gallium arsenide source follower FET logic family with diodes for preventing leakage currents' [patent_app_type] => 1 [patent_app_number] => 8/225518 [patent_app_country] => US [patent_app_date] => 1994-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 3805 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/451/05451890.pdf [firstpage_image] =>[orig_patent_app_number] => 225518 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3469703 [patent_doc_number] => 05392164 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-21 [patent_title] => 'Dubbing system' [patent_app_type] => 1 [patent_app_number] => 8/223309 [patent_app_country] => US [patent_app_date] => 1994-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 34 [patent_no_of_words] => 6918 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/392/05392164.pdf [firstpage_image] =>[orig_patent_app_number] => 223309 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3423584 [patent_doc_number] => 05434517 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-18 [patent_title] => 'ECL output buffer with a MOS transistor used for tristate enable' [patent_app_type] => 1 [patent_app_number] => 8/215174 [patent_app_country] => US [patent_app_date] => 1994-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4972 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 330 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/434/05434517.pdf [firstpage_image] =>[orig_patent_app_number] => 215174 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3569520 [patent_doc_number] => 05483178 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-09 [patent_title] => 'Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers' [patent_app_type] => 1 [patent_app_number] => 8/207012 [patent_app_country] => US [patent_app_date] => 1994-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2059 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/483/05483178.pdf [firstpage_image] =>[orig_patent_app_number] => 207012 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3562788 [patent_doc_number] => 05502400 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'Logically configurable impedance matching input terminators for VLSI' [patent_app_type] => 1 [patent_app_number] => 8/196675 [patent_app_country] => US [patent_app_date] => 1994-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3014 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/502/05502400.pdf [firstpage_image] =>[orig_patent_app_number] => 196675 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3553239 [patent_doc_number] => 05546021 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-13 [patent_title] => '3-state bicmos output buffer having power down capability' [patent_app_type] => 1 [patent_app_number] => 8/194974 [patent_app_country] => US [patent_app_date] => 1994-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4262 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/546/05546021.pdf [firstpage_image] =>[orig_patent_app_number] => 194974 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3516416 [patent_doc_number] => 05563530 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-08 [patent_title] => 'Multi-function resonant tunneling logic gate and method of performing binary and multi-valued logic' [patent_app_type] => 1 [patent_app_number] => 8/194756 [patent_app_country] => US [patent_app_date] => 1994-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 4733 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/563/05563530.pdf [firstpage_image] =>[orig_patent_app_number] => 194756 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3461126 [patent_doc_number] => 05402013 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-28 [patent_title] => 'Common mode logic multiplexer configuration' [patent_app_type] => 1 [patent_app_number] => 8/191878 [patent_app_country] => US [patent_app_date] => 1994-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3127 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/402/05402013.pdf [firstpage_image] =>[orig_patent_app_number] => 191878 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3488369 [patent_doc_number] => 05446403 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-29 [patent_title] => 'Power on reset signal circuit with clock inhibit and delayed reset' [patent_app_type] => 1 [patent_app_number] => 8/192178 [patent_app_country] => US [patent_app_date] => 1994-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4483 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/446/05446403.pdf [firstpage_image] =>[orig_patent_app_number] => 192178 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3465026 [patent_doc_number] => 05442308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-15 [patent_title] => 'Dynamic decoder circuit operative at low frequency clock signals without data destruction' [patent_app_type] => 1 [patent_app_number] => 8/190477 [patent_app_country] => US [patent_app_date] => 1994-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4973 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/442/05442308.pdf [firstpage_image] =>[orig_patent_app_number] => 190477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3488223 [patent_doc_number] => 05457579 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-10 [patent_title] => 'Apparatus for recording each editing unit of video and audio signals in an isolated area on a recording medium' [patent_app_type] => 1 [patent_app_number] => 8/173477 [patent_app_country] => US [patent_app_date] => 1993-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 6131 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/457/05457579.pdf [firstpage_image] =>[orig_patent_app_number] => 173477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3112003 [patent_doc_number] => 05418479 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-23 [patent_title] => 'Method and circuitry for generating a safe address transition pulse in a memory device' [patent_app_type] => 1 [patent_app_number] => 8/174877 [patent_app_country] => US [patent_app_date] => 1993-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6403 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/418/05418479.pdf [firstpage_image] =>[orig_patent_app_number] => 174877 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3433247 [patent_doc_number] => 05455525 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-03 [patent_title] => 'Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array' [patent_app_type] => 1 [patent_app_number] => 8/162678 [patent_app_country] => US [patent_app_date] => 1993-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7592 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/455/05455525.pdf [firstpage_image] =>[orig_patent_app_number] => 162678 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3121087 [patent_doc_number] => 05414568 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-09 [patent_title] => 'Variable speed digital signal reproducing apparatus' [patent_app_type] => 1 [patent_app_number] => 8/156941 [patent_app_country] => US [patent_app_date] => 1993-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 8566 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/414/05414568.pdf [firstpage_image] =>[orig_patent_app_number] => 156941 [rel_patent_id] =>[rel_patent_doc_number] =>)