John D Pak

Array ( [id] => 3107960 [patent_doc_number] => 05448187 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-05 [patent_title] => 'Antifuse programming method and circuit which supplies a steady current after a programming voltage has dropped' [patent_app_type] => 1 [patent_app_number] => 8/152183 [patent_app_country] => US [patent_app_date] => 1993-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3595 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/448/05448187.pdf [firstpage_image] =>[orig_patent_app_number] => 152183 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3484329 [patent_doc_number] => 05399920 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-21 [patent_title] => 'CMOS driver which uses a higher voltage to compensate for threshold loss of the pull-up NFET' [patent_app_type] => 1 [patent_app_number] => 8/149576 [patent_app_country] => US [patent_app_date] => 1993-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2682 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/399/05399920.pdf [firstpage_image] =>[orig_patent_app_number] => 149576 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3586828 [patent_doc_number] => 05498975 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-12 [patent_title] => 'Implementation of redundancy on a programmable logic device' [patent_app_type] => 1 [patent_app_number] => 8/147601 [patent_app_country] => US [patent_app_date] => 1993-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4227 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/498/05498975.pdf [firstpage_image] =>[orig_patent_app_number] => 147601 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3467144 [patent_doc_number] => 05469085 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-21 [patent_title] => 'Source follower using two pairs of NMOS and PMOS transistors' [patent_app_type] => 1 [patent_app_number] => 8/087675 [patent_app_country] => US [patent_app_date] => 1993-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4252 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/469/05469085.pdf [firstpage_image] =>[orig_patent_app_number] => 087675 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3514679 [patent_doc_number] => 05587668 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-24 [patent_title] => 'Semiconductor devices utilizing neuron MOS transistors' [patent_app_type] => 1 [patent_app_number] => 8/119157 [patent_app_country] => US [patent_app_date] => 1993-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 123 [patent_no_of_words] => 27262 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/587/05587668.pdf [firstpage_image] =>[orig_patent_app_number] => 119157 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3592029 [patent_doc_number] => 05552724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-03 [patent_title] => 'Power-down reference circuit for ECL gate circuitry' [patent_app_type] => 1 [patent_app_number] => 8/122273 [patent_app_country] => US [patent_app_date] => 1993-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3907 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/552/05552724.pdf [firstpage_image] =>[orig_patent_app_number] => 122273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3104556 [patent_doc_number] => 05315178 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-24 [patent_title] => 'IC which can be used as a programmable logic cell array or as a register file' [patent_app_type] => 1 [patent_app_number] => 8/113578 [patent_app_country] => US [patent_app_date] => 1993-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 6570 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/315/05315178.pdf [firstpage_image] =>[orig_patent_app_number] => 113578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3130158 [patent_doc_number] => 05436575 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-25 [patent_title] => 'Programmable logic array integrated circuits' [patent_app_type] => 1 [patent_app_number] => 8/111693 [patent_app_country] => US [patent_app_date] => 1993-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 8574 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 561 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/436/05436575.pdf [firstpage_image] =>[orig_patent_app_number] => 111693 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3458517 [patent_doc_number] => 05378945 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-03 [patent_title] => 'Voltage level converting buffer circuit' [patent_app_type] => 1 [patent_app_number] => 8/097781 [patent_app_country] => US [patent_app_date] => 1993-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3619 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/378/05378945.pdf [firstpage_image] =>[orig_patent_app_number] => 097781 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3484371 [patent_doc_number] => 05399923 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-21 [patent_title] => 'Field programmable gate array device with antifuse overcurrent protection' [patent_app_type] => 1 [patent_app_number] => 8/096324 [patent_app_country] => US [patent_app_date] => 1993-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3359 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/399/05399923.pdf [firstpage_image] =>[orig_patent_app_number] => 096324 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3130211 [patent_doc_number] => 05436578 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-25 [patent_title] => 'CMOS output pad driver with variable drive currents ESD protection and improved leakage current behavior' [patent_app_type] => 1 [patent_app_number] => 8/091705 [patent_app_country] => US [patent_app_date] => 1993-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3388 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/436/05436578.pdf [firstpage_image] =>[orig_patent_app_number] => 091705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3066438 [patent_doc_number] => 05339199 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-16 [patent_title] => 'Still video device with selectable successive erasure of audio and/or video tracks' [patent_app_type] => 1 [patent_app_number] => 8/088589 [patent_app_country] => US [patent_app_date] => 1993-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5182 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/339/05339199.pdf [firstpage_image] =>[orig_patent_app_number] => 088589 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3447610 [patent_doc_number] => 05397943 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-14 [patent_title] => 'Clock distribution method and apparatus for high speed circuits with low skew using counterpropaging true and complement re-generated clock signals with predetermined ramp shapes' [patent_app_type] => 1 [patent_app_number] => 8/088982 [patent_app_country] => US [patent_app_date] => 1993-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5767 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 507 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/397/05397943.pdf [firstpage_image] =>[orig_patent_app_number] => 088982 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3418090 [patent_doc_number] => 05444394 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-22 [patent_title] => 'PLD with selective inputs from local and global conductors' [patent_app_type] => 1 [patent_app_number] => 8/088973 [patent_app_country] => US [patent_app_date] => 1993-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2905 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/444/05444394.pdf [firstpage_image] =>[orig_patent_app_number] => 088973 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3104611 [patent_doc_number] => 05315181 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-24 [patent_title] => 'Circuit for synchronous, glitch-free clock switching' [patent_app_type] => 1 [patent_app_number] => 8/087980 [patent_app_country] => US [patent_app_date] => 1993-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2983 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 362 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/315/05315181.pdf [firstpage_image] =>[orig_patent_app_number] => 087980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3448130 [patent_doc_number] => 05467033 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-14 [patent_title] => 'Chip clock skew control method and apparatus' [patent_app_type] => 1 [patent_app_number] => 8/087226 [patent_app_country] => US [patent_app_date] => 1993-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2806 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/467/05467033.pdf [firstpage_image] =>[orig_patent_app_number] => 087226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3484357 [patent_doc_number] => 05399922 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-21 [patent_title] => 'Macrocell comprised of two look-up tables and two flip-flops' [patent_app_type] => 1 [patent_app_number] => 8/086420 [patent_app_country] => US [patent_app_date] => 1993-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2679 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/399/05399922.pdf [firstpage_image] =>[orig_patent_app_number] => 086420 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3428460 [patent_doc_number] => 05459412 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-17 [patent_title] => 'BiCMOS circuit for translation of ECL logic levels to MOS logic levels' [patent_app_type] => 1 [patent_app_number] => 8/086503 [patent_app_country] => US [patent_app_date] => 1993-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5649 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/459/05459412.pdf [firstpage_image] =>[orig_patent_app_number] => 086503 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3479709 [patent_doc_number] => 05428311 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-27 [patent_title] => 'Fuse circuitry to control the propagation delay of an IC' [patent_app_type] => 1 [patent_app_number] => 8/085580 [patent_app_country] => US [patent_app_date] => 1993-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2227 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/428/05428311.pdf [firstpage_image] =>[orig_patent_app_number] => 085580 [rel_patent_id] =>[rel_patent_doc_number] =>)