Search

John D Pak

Examiner (ID: 1394, Phone: (571)272-0620 , Office: P/1616 )

Most Active Art Unit
1616
Art Unit(s)
1209, 1616, 1621, 1699, 2899
Total Applications
2636
Issued Applications
1470
Pending Applications
229
Abandoned Applications
937

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3415253 [patent_doc_number] => 05461330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-24 [patent_title] => 'Bus settle time by using previous bus state to condition bus at all receiving locations' [patent_app_type] => 1 [patent_app_number] => 8/080375 [patent_app_country] => US [patent_app_date] => 1993-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 16603 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/461/05461330.pdf [firstpage_image] =>[orig_patent_app_number] => 080375 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/080375
Bus settle time by using previous bus state to condition bus at all receiving locations Jun 17, 1993 Issued
08/073679 PROGRAMMABLE CMOS BUS AND TRANSMISSION LINE DRIVER Jun 7, 1993 Pending
Array ( [id] => 3425910 [patent_doc_number] => 05389836 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-14 [patent_title] => 'Branch isolation circuit for cascode voltage switch logic' [patent_app_type] => 1 [patent_app_number] => 8/072276 [patent_app_country] => US [patent_app_date] => 1993-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3462 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/389/05389836.pdf [firstpage_image] =>[orig_patent_app_number] => 072276 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/072276
Branch isolation circuit for cascode voltage switch logic Jun 3, 1993 Issued
Array ( [id] => 3007010 [patent_doc_number] => 05371414 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-06 [patent_title] => 'Simultaneous multiple antifuse programming method' [patent_app_type] => 1 [patent_app_number] => 8/067381 [patent_app_country] => US [patent_app_date] => 1993-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3334 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/371/05371414.pdf [firstpage_image] =>[orig_patent_app_number] => 067381 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/067381
Simultaneous multiple antifuse programming method May 25, 1993 Issued
08/066632 ELECTRONIC STILL CAMERA AND MAGNETIC DISK May 24, 1993 Pending
Array ( [id] => 3454304 [patent_doc_number] => 05424656 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-13 [patent_title] => 'Continuous superconductor to semiconductor converter circuit' [patent_app_type] => 1 [patent_app_number] => 8/059476 [patent_app_country] => US [patent_app_date] => 1993-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 7005 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/424/05424656.pdf [firstpage_image] =>[orig_patent_app_number] => 059476 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/059476
Continuous superconductor to semiconductor converter circuit May 6, 1993 Issued
Array ( [id] => 3491652 [patent_doc_number] => 05426376 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-20 [patent_title] => 'Noise isolated I/O buffer that uses two separate power supplies' [patent_app_type] => 1 [patent_app_number] => 8/052442 [patent_app_country] => US [patent_app_date] => 1993-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 4297 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/426/05426376.pdf [firstpage_image] =>[orig_patent_app_number] => 052442 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/052442
Noise isolated I/O buffer that uses two separate power supplies Apr 22, 1993 Issued
08/052134 MULTI-FUNCTIONAL PROGRAMMABLE OUTPUT PIN FOR INTEGRATED CIRCUIT WITH IMPEDANCE PROGRAMMING CAPABILITY Apr 21, 1993 Pending
Array ( [id] => 3069126 [patent_doc_number] => 05311077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-10 [patent_title] => 'Power supply, temperature, and load capacitance compensating, controlled slew rate output buffer' [patent_app_type] => 1 [patent_app_number] => 8/049793 [patent_app_country] => US [patent_app_date] => 1993-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4827 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/311/05311077.pdf [firstpage_image] =>[orig_patent_app_number] => 049793 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/049793
Power supply, temperature, and load capacitance compensating, controlled slew rate output buffer Apr 20, 1993 Issued
08/049543 A PROGRAMMABLE LOGIC DEVICE HAVING FAST PROGRAMMABLE LOGIC ARRAY BLOCKS AND A CENTRAL GLOBAL INTERCONNECT ARRAY Apr 18, 1993 Pending
08/049742 COMPLEMENTARY-SIGNAL BICMOS LINE DRIVER WITH LOW SKEW Apr 18, 1993 Pending
08/049741 BICMOS OUTPUT DRIVER WITH REDUCED STATIC POWER CONSUMPTION Apr 18, 1993 Pending
Array ( [id] => 3486934 [patent_doc_number] => 05406215 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-11 [patent_title] => 'Open drain driver circuit which eliminates overshoot caused by parasitic capacitances' [patent_app_type] => 1 [patent_app_number] => 8/045937 [patent_app_country] => US [patent_app_date] => 1993-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 4802 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/406/05406215.pdf [firstpage_image] =>[orig_patent_app_number] => 045937 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/045937
Open drain driver circuit which eliminates overshoot caused by parasitic capacitances Apr 11, 1993 Issued
Array ( [id] => 3033662 [patent_doc_number] => 05349249 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-20 [patent_title] => 'Programmable logic device having security elements located amongst configuration bit location to prevent unauthorized reading' [patent_app_type] => 1 [patent_app_number] => 8/043882 [patent_app_country] => US [patent_app_date] => 1993-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2192 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/349/05349249.pdf [firstpage_image] =>[orig_patent_app_number] => 043882 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/043882
Programmable logic device having security elements located amongst configuration bit location to prevent unauthorized reading Apr 6, 1993 Issued
Array ( [id] => 3041428 [patent_doc_number] => 05373203 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-13 [patent_title] => 'Decoder and latching circuit with differential outputs' [patent_app_type] => 1 [patent_app_number] => 8/043078 [patent_app_country] => US [patent_app_date] => 1993-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3549 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/373/05373203.pdf [firstpage_image] =>[orig_patent_app_number] => 043078 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/043078
Decoder and latching circuit with differential outputs Apr 4, 1993 Issued
Array ( [id] => 3043820 [patent_doc_number] => 05376844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-27 [patent_title] => 'Programmable logic device with multiplexer-based programmable interconnections' [patent_app_type] => 1 [patent_app_number] => 8/039944 [patent_app_country] => US [patent_app_date] => 1993-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3419 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/376/05376844.pdf [firstpage_image] =>[orig_patent_app_number] => 039944 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/039944
Programmable logic device with multiplexer-based programmable interconnections Mar 28, 1993 Issued
Array ( [id] => 3007156 [patent_doc_number] => 05371422 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-06 [patent_title] => 'Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnections between logic elements' [patent_app_type] => 1 [patent_app_number] => 8/038787 [patent_app_country] => US [patent_app_date] => 1993-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4047 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/371/05371422.pdf [firstpage_image] =>[orig_patent_app_number] => 038787 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/038787
Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnections between logic elements Mar 28, 1993 Issued
Array ( [id] => 3007137 [patent_doc_number] => 05371421 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-06 [patent_title] => 'Low power BiMOS amplifier and ECL-CMOS level converter' [patent_app_type] => 1 [patent_app_number] => 8/029686 [patent_app_country] => US [patent_app_date] => 1993-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3230 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/371/05371421.pdf [firstpage_image] =>[orig_patent_app_number] => 029686 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/029686
Low power BiMOS amplifier and ECL-CMOS level converter Mar 10, 1993 Issued
08/028046 PROGRAMMABLE LOGIC DEVICE HAVING A GLOBAL INTERCONNECT MATRIX USED TO INTERCONNECT LOGIC BLOCKS Mar 7, 1993 Pending
Array ( [id] => 3565979 [patent_doc_number] => 05519812 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-05-21 [patent_title] => 'Ferrelectric adaptive-learning type product-sum operation circuit element and circuit using such element' [patent_app_type] => 1 [patent_app_number] => 8/026779 [patent_app_country] => US [patent_app_date] => 1993-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5040 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/519/05519812.pdf [firstpage_image] =>[orig_patent_app_number] => 026779 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/026779
Ferrelectric adaptive-learning type product-sum operation circuit element and circuit using such element Mar 4, 1993 Issued
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