John D Pak

Array ( [id] => 3104287 [patent_doc_number] => 05315163 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-24 [patent_title] => 'Analogic neuronal network' [patent_app_type] => 1 [patent_app_number] => 8/021077 [patent_app_country] => US [patent_app_date] => 1993-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4748 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/315/05315163.pdf [firstpage_image] =>[orig_patent_app_number] => 021077 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3112888 [patent_doc_number] => 05408145 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-18 [patent_title] => 'Low power consumption and high speed NOR gate integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/017084 [patent_app_country] => US [patent_app_date] => 1993-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1994 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/408/05408145.pdf [firstpage_image] =>[orig_patent_app_number] => 017084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3060428 [patent_doc_number] => 05357153 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-18 [patent_title] => 'Macrocell with product-term cascade and improved flip flop utilization' [patent_app_type] => 1 [patent_app_number] => 8/010378 [patent_app_country] => US [patent_app_date] => 1993-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2931 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/357/05357153.pdf [firstpage_image] =>[orig_patent_app_number] => 010378 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3097811 [patent_doc_number] => 05313120 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-17 [patent_title] => 'Address buffer with ATD generation' [patent_app_type] => 1 [patent_app_number] => 8/007879 [patent_app_country] => US [patent_app_date] => 1993-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6084 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/313/05313120.pdf [firstpage_image] =>[orig_patent_app_number] => 007879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3012858 [patent_doc_number] => 05355031 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-11 [patent_title] => 'Complementary logic with n-channel output transistors' [patent_app_type] => 1 [patent_app_number] => 7/999540 [patent_app_country] => US [patent_app_date] => 1992-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 4451 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/355/05355031.pdf [firstpage_image] =>[orig_patent_app_number] => 999540 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3033702 [patent_doc_number] => 05349253 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-20 [patent_title] => 'Logic translator interfacing between five-volt TTL/CMOS and three-volt CML' [patent_app_type] => 1 [patent_app_number] => 7/992544 [patent_app_country] => US [patent_app_date] => 1992-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6433 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/349/05349253.pdf [firstpage_image] =>[orig_patent_app_number] => 992544 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3020198 [patent_doc_number] => 05341046 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-23 [patent_title] => 'Threshold controlled input circuit for an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 7/986184 [patent_app_country] => US [patent_app_date] => 1992-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4593 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 372 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/341/05341046.pdf [firstpage_image] =>[orig_patent_app_number] => 986184 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3032188 [patent_doc_number] => 05317206 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-31 [patent_title] => 'Buffer circuit using capacitors to control the slow rate of a driver transistor' [patent_app_type] => 1 [patent_app_number] => 7/980877 [patent_app_country] => US [patent_app_date] => 1992-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 11228 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/317/05317206.pdf [firstpage_image] =>[orig_patent_app_number] => 980877 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3423542 [patent_doc_number] => 05434514 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-18 [patent_title] => 'Programmable logic devices with spare circuits for replacement of defects' [patent_app_type] => 1 [patent_app_number] => 7/979003 [patent_app_country] => US [patent_app_date] => 1992-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4311 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/434/05434514.pdf [firstpage_image] =>[orig_patent_app_number] => 979003 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3080697 [patent_doc_number] => 05323068 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-21 [patent_title] => 'Low power low temperature ECL output driver circuit' [patent_app_type] => 1 [patent_app_number] => 7/977812 [patent_app_country] => US [patent_app_date] => 1992-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3182 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/323/05323068.pdf [firstpage_image] =>[orig_patent_app_number] => 977812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3425875 [patent_doc_number] => 05389834 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-14 [patent_title] => 'Output buffer circuit having a DC driver and an AC driver' [patent_app_type] => 1 [patent_app_number] => 7/975482 [patent_app_country] => US [patent_app_date] => 1992-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 84 [patent_no_of_words] => 12626 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/389/05389834.pdf [firstpage_image] =>[orig_patent_app_number] => 975482 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3041153 [patent_doc_number] => 05300832 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-05 [patent_title] => 'Voltage interfacing buffer with isolation transistors used for overvoltage protection' [patent_app_type] => 1 [patent_app_number] => 7/974100 [patent_app_country] => US [patent_app_date] => 1992-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3614 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/300/05300832.pdf [firstpage_image] =>[orig_patent_app_number] => 974100 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3133381 [patent_doc_number] => 05381515 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-10 [patent_title] => 'Two layer neural network comprised of neurons with improved input range and input offset' [patent_app_type] => 1 [patent_app_number] => 7/972024 [patent_app_country] => US [patent_app_date] => 1992-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 31 [patent_no_of_words] => 12860 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 650 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/381/05381515.pdf [firstpage_image] =>[orig_patent_app_number] => 972024 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3032325 [patent_doc_number] => 05317213 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-31 [patent_title] => 'Level converter with delay circuitry used to increase switching speed' [patent_app_type] => 1 [patent_app_number] => 7/961979 [patent_app_country] => US [patent_app_date] => 1992-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 9943 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/317/05317213.pdf [firstpage_image] =>[orig_patent_app_number] => 961979 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3084038 [patent_doc_number] => 05321321 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-14 [patent_title] => 'Emitter-coupled logic (ECL) circuit with an inductively coupled output stage for enhanced operating speed' [patent_app_type] => 1 [patent_app_number] => 7/937388 [patent_app_country] => US [patent_app_date] => 1992-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 3121 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/321/05321321.pdf [firstpage_image] =>[orig_patent_app_number] => 937388 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3098309 [patent_doc_number] => 05291076 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-01 [patent_title] => 'Decoder/comparator and method of operation' [patent_app_type] => 1 [patent_app_number] => 7/937018 [patent_app_country] => US [patent_app_date] => 1992-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 6720 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/291/05291076.pdf [firstpage_image] =>[orig_patent_app_number] => 937018 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3041074 [patent_doc_number] => 05300828 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-05 [patent_title] => 'Slew rate limited output buffer with bypass circuitry' [patent_app_type] => 1 [patent_app_number] => 7/938399 [patent_app_country] => US [patent_app_date] => 1992-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2951 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/300/05300828.pdf [firstpage_image] =>[orig_patent_app_number] => 938399 [rel_patent_id] =>[rel_patent_doc_number] =>)