Application number | Title of the application | Filing Date | Status |
---|
Array
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[id] => 3077602
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[patent_kind] => NA
[patent_issue_date] => 1994-11-15
[patent_title] => 'Semiconductor logic circuits with diodes and amplitude limiter'
[patent_app_type] => 1
[patent_app_number] => 7/937095
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[patent_app_date] => 1992-08-31
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[firstpage_image] =>[orig_patent_app_number] => 937095
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/937095 | Semiconductor logic circuits with diodes and amplitude limiter | Aug 30, 1992 | Issued |
Array
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[patent_doc_number] => 05336937
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-08-09
[patent_title] => 'Programmable analog synapse and neural networks incorporating same'
[patent_app_type] => 1
[patent_app_number] => 7/937804
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[patent_app_date] => 1992-08-28
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[pdf_file] => patents/05/336/05336937.pdf
[firstpage_image] =>[orig_patent_app_number] => 937804
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/937804 | Programmable analog synapse and neural networks incorporating same | Aug 27, 1992 | Issued |
Array
(
[id] => 2968033
[patent_doc_number] => 05264745
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-23
[patent_title] => 'Recovering phase and data from distorted duty cycles caused by ECL-to-CMOS translator'
[patent_app_type] => 1
[patent_app_number] => 7/935886
[patent_app_country] => US
[patent_app_date] => 1992-08-28
[patent_effective_date] => 0000-00-00
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07/936822 | PROGRAMMABLE LOGIC CIRCUITRY AND METHODS | Aug 27, 1992 | Abandoned |
07/934702 | GALLIUM ARSENIDE SOURCE FOLLOWER FET LOGIC FAMILY WITH DIODES FOR PREVENTING LEAKAGE CURRENTS | Aug 23, 1992 | Abandoned |
Array
(
[id] => 3447596
[patent_doc_number] => 05397942
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-14
[patent_title] => 'Driver circuit for a plurality of outputs'
[patent_app_type] => 1
[patent_app_number] => 7/933709
[patent_app_country] => US
[patent_app_date] => 1992-08-24
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Array
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[patent_doc_number] => 05343081
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-08-30
[patent_title] => 'Synapse circuit which utilizes ballistic electron beams in two-dimensional electron gas'
[patent_app_type] => 1
[patent_app_number] => 7/933118
[patent_app_country] => US
[patent_app_date] => 1992-08-21
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[firstpage_image] =>[orig_patent_app_number] => 933118
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/933118 | Synapse circuit which utilizes ballistic electron beams in two-dimensional electron gas | Aug 20, 1992 | Issued |
Array
(
[id] => 3015420
[patent_doc_number] => 05281868
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-25
[patent_title] => 'Memory redundancy addressing circuit for adjacent columns in a memory'
[patent_app_type] => 1
[patent_app_number] => 7/932386
[patent_app_country] => US
[patent_app_date] => 1992-08-18
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[firstpage_image] =>[orig_patent_app_number] => 932386
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/932386 | Memory redundancy addressing circuit for adjacent columns in a memory | Aug 17, 1992 | Issued |
Array
(
[id] => 3070387
[patent_doc_number] => 05294845
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-15
[patent_title] => 'Data processor having an output terminal with selectable output impedances'
[patent_app_type] => 1
[patent_app_number] => 7/931187
[patent_app_country] => US
[patent_app_date] => 1992-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[firstpage_image] =>[orig_patent_app_number] => 931187
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/931187 | Data processor having an output terminal with selectable output impedances | Aug 16, 1992 | Issued |
Array
(
[id] => 3052464
[patent_doc_number] => 05304872
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-04-19
[patent_title] => 'TTL/CMOS input buffer operable with three volt and five volt power supplies'
[patent_app_type] => 1
[patent_app_number] => 7/927593
[patent_app_country] => US
[patent_app_date] => 1992-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 4857
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[firstpage_image] =>[orig_patent_app_number] => 927593
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/927593 | TTL/CMOS input buffer operable with three volt and five volt power supplies | Aug 9, 1992 | Issued |
Array
(
[id] => 3485637
[patent_doc_number] => 05457409
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-10-10
[patent_title] => 'Architecture of a multiple array high density programmable logic device with a plurality of programmable switch matrices'
[patent_app_type] => 1
[patent_app_number] => 7/924685
[patent_app_country] => US
[patent_app_date] => 1992-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 29
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[firstpage_image] =>[orig_patent_app_number] => 924685
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/924685 | Architecture of a multiple array high density programmable logic device with a plurality of programmable switch matrices | Aug 2, 1992 | Issued |
07/924267 | MULTIPLE ARRAY PROGRAMMABLE LOGIC DEVICE WITH A PLURALITY OF PROGRAMMABLE SWITCH MATRICES | Aug 2, 1992 | Abandoned |
Array
(
[id] => 3526597
[patent_doc_number] => 05489857
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-06
[patent_title] => 'Flexible synchronous/asynchronous cell structure for a high density programmable logic device'
[patent_app_type] => 1
[patent_app_number] => 7/924201
[patent_app_country] => US
[patent_app_date] => 1992-08-03
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[firstpage_image] =>[orig_patent_app_number] => 924201
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/924201 | Flexible synchronous/asynchronous cell structure for a high density programmable logic device | Aug 2, 1992 | Issued |
Array
(
[id] => 3012102
[patent_doc_number] => 05331215
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-19
[patent_title] => 'Electrically adaptable neural network with post-processing circuitry'
[patent_app_type] => 1
[patent_app_number] => 7/922535
[patent_app_country] => US
[patent_app_date] => 1992-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[patent_no_of_words] => 11004
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[pdf_file] => patents/05/331/05331215.pdf
[firstpage_image] =>[orig_patent_app_number] => 922535
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/922535 | Electrically adaptable neural network with post-processing circuitry | Jul 29, 1992 | Issued |
07/914294 | CONTROLLED SLEW RATE OUTPUT BUFFER | Jul 14, 1992 | Abandoned |
07/913691 | ELECTRICALLY ADAPTABLE NEURAL NETWORK | Jul 13, 1992 | Abandoned |
Array
(
[id] => 3104466
[patent_doc_number] => 05315173
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-24
[patent_title] => 'Data buffer circuit with delay circuit to increase the length of a switching transition period during data signal inversion'
[patent_app_type] => 1
[patent_app_number] => 7/898535
[patent_app_country] => US
[patent_app_date] => 1992-06-15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/898535 | Data buffer circuit with delay circuit to increase the length of a switching transition period during data signal inversion | Jun 14, 1992 | Issued |
07/884156 | LEVEL CONVERSION OUTPUT CIRCUIT WITH REDUCED POWER CONSUMPTION | May 17, 1992 | Abandoned |
07/883843 | PROGRAMMABLE LOGIC DEVICE MACROCELL WITH AN EXCLUSIVE FEEDBACK LINE AND AN EXCLUSIVE EXTERNAL INPUT LINE FOR A STATE COUNTER OR REGISTERED SUM-OF-PRODUCTS SIGNAL | May 14, 1992 | Abandoned |
Array
(
[id] => 2973992
[patent_doc_number] => 05258665
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-02
[patent_title] => 'AC Miller-Killer circuit for L.fwdarw.Z transitions'
[patent_app_type] => 1
[patent_app_number] => 7/881540
[patent_app_country] => US
[patent_app_date] => 1992-05-12
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[pdf_file] => patents/05/258/05258665.pdf
[firstpage_image] =>[orig_patent_app_number] => 881540
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/881540 | AC Miller-Killer circuit for L.fwdarw.Z transitions | May 11, 1992 | Issued |