![](/images/general/no_picture/200_user.png)
John D Pak
Examiner (ID: 1394, Phone: (571)272-0620 , Office: P/1616 )
Most Active Art Unit | 1616 |
Art Unit(s) | 1209, 1616, 1621, 1699, 2899 |
Total Applications | 2636 |
Issued Applications | 1470 |
Pending Applications | 229 |
Abandoned Applications | 937 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 2936533
[patent_doc_number] => 05233239
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-03
[patent_title] => 'ECL circuit with feedback circuitry for increased speed'
[patent_app_type] => 1
[patent_app_number] => 7/880835
[patent_app_country] => US
[patent_app_date] => 1992-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 1984
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/233/05233239.pdf
[firstpage_image] =>[orig_patent_app_number] => 880835
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/880835 | ECL circuit with feedback circuitry for increased speed | May 10, 1992 | Issued |
Array
(
[id] => 2942537
[patent_doc_number] => 05260611
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-09
[patent_title] => 'Programmable logic array having local and long distance conductors'
[patent_app_type] => 1
[patent_app_number] => 7/880942
[patent_app_country] => US
[patent_app_date] => 1992-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 5439
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/260/05260611.pdf
[firstpage_image] =>[orig_patent_app_number] => 880942
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/880942 | Programmable logic array having local and long distance conductors | May 7, 1992 | Issued |
Array
(
[id] => 2974035
[patent_doc_number] => 05258668
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-02
[patent_title] => 'Programmable logic array integrated circuits with cascade connections between logic modules'
[patent_app_type] => 1
[patent_app_number] => 7/880888
[patent_app_country] => US
[patent_app_date] => 1992-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2485
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/258/05258668.pdf
[firstpage_image] =>[orig_patent_app_number] => 880888
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/880888 | Programmable logic array integrated circuits with cascade connections between logic modules | May 7, 1992 | Issued |
Array
(
[id] => 3017984
[patent_doc_number] => 05309045
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-03
[patent_title] => 'Configurable logic element with independently clocked outputs and node observation circuitry'
[patent_app_type] => 1
[patent_app_number] => 7/880591
[patent_app_country] => US
[patent_app_date] => 1992-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 24
[patent_no_of_words] => 8902
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 15
[patent_words_short_claim] => 33
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/309/05309045.pdf
[firstpage_image] =>[orig_patent_app_number] => 880591
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/880591 | Configurable logic element with independently clocked outputs and node observation circuitry | May 7, 1992 | Issued |
Array
(
[id] => 3014944
[patent_doc_number] => 05276362
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-04
[patent_title] => 'BiCMOS TTL to CMOS level translator'
[patent_app_type] => 1
[patent_app_number] => 7/879646
[patent_app_country] => US
[patent_app_date] => 1992-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1849
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/276/05276362.pdf
[firstpage_image] =>[orig_patent_app_number] => 879646
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/879646 | BiCMOS TTL to CMOS level translator | May 5, 1992 | Issued |
Array
(
[id] => 3101939
[patent_doc_number] => 05313338
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-17
[patent_title] => 'Editing device which selectively edits a section of a helical track'
[patent_app_type] => 1
[patent_app_number] => 7/865584
[patent_app_country] => US
[patent_app_date] => 1992-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3458
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 374
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/313/05313338.pdf
[firstpage_image] =>[orig_patent_app_number] => 865584
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/865584 | Editing device which selectively edits a section of a helical track | Apr 8, 1992 | Issued |
Array
(
[id] => 2972242
[patent_doc_number] => 05264969
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-23
[patent_title] => 'Tape editing apparatus with automatic tracking adjustment prior to recording'
[patent_app_type] => 1
[patent_app_number] => 7/865952
[patent_app_country] => US
[patent_app_date] => 1992-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3836
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/264/05264969.pdf
[firstpage_image] =>[orig_patent_app_number] => 865952
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/865952 | Tape editing apparatus with automatic tracking adjustment prior to recording | Apr 8, 1992 | Issued |
07/861619 | CHARACTER EDITING SYSTEM FOR VCR | Mar 31, 1992 | Abandoned |
Array
(
[id] => 3557885
[patent_doc_number] => 05493232
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-20
[patent_title] => 'Disturbance immune output buffer with switch and hold stages'
[patent_app_type] => 1
[patent_app_number] => 7/850360
[patent_app_country] => US
[patent_app_date] => 1992-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2251
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 331
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/493/05493232.pdf
[firstpage_image] =>[orig_patent_app_number] => 850360
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/850360 | Disturbance immune output buffer with switch and hold stages | Mar 10, 1992 | Issued |
Array
(
[id] => 2955018
[patent_doc_number] => 05262687
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-16
[patent_title] => 'Decoder circuit with bypass circuitry and reduced input capacitance for greater speed'
[patent_app_type] => 1
[patent_app_number] => 7/848257
[patent_app_country] => US
[patent_app_date] => 1992-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2800
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/262/05262687.pdf
[firstpage_image] =>[orig_patent_app_number] => 848257
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/848257 | Decoder circuit with bypass circuitry and reduced input capacitance for greater speed | Mar 8, 1992 | Issued |
Array
(
[id] => 3052429
[patent_doc_number] => 05304870
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-04-19
[patent_title] => 'Source electrode-connected type buffer circuit having LDD structure and breakdown voltage protection'
[patent_app_type] => 1
[patent_app_number] => 7/846162
[patent_app_country] => US
[patent_app_date] => 1992-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 1757
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/304/05304870.pdf
[firstpage_image] =>[orig_patent_app_number] => 846162
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/846162 | Source electrode-connected type buffer circuit having LDD structure and breakdown voltage protection | Mar 4, 1992 | Issued |
07/816439 | BUFFERED COMPLEMENTARY LOGIC | Dec 30, 1991 | Abandoned |
Array
(
[id] => 2912073
[patent_doc_number] => 05216293
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-06-01
[patent_title] => 'CMOS output buffer with pre-drive circuitry to control slew rate of main drive transistors'
[patent_app_type] => 1
[patent_app_number] => 7/814438
[patent_app_country] => US
[patent_app_date] => 1991-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 2860
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/216/05216293.pdf
[firstpage_image] =>[orig_patent_app_number] => 814438
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/814438 | CMOS output buffer with pre-drive circuitry to control slew rate of main drive transistors | Dec 29, 1991 | Issued |
Array
(
[id] => 2925415
[patent_doc_number] => 05235222
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-10
[patent_title] => 'Output circuit and interface system comprising the same'
[patent_app_type] => 1
[patent_app_number] => 7/813627
[patent_app_country] => US
[patent_app_date] => 1991-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 3503
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/235/05235222.pdf
[firstpage_image] =>[orig_patent_app_number] => 813627
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/813627 | Output circuit and interface system comprising the same | Dec 25, 1991 | Issued |
Array
(
[id] => 2899852
[patent_doc_number] => 05241225
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-31
[patent_title] => 'Level conversion circuit having improved control and speed of switching from high to low level converter outputs'
[patent_app_type] => 1
[patent_app_number] => 7/812918
[patent_app_country] => US
[patent_app_date] => 1991-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 19
[patent_no_of_words] => 5145
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/241/05241225.pdf
[firstpage_image] =>[orig_patent_app_number] => 812918
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/812918 | Level conversion circuit having improved control and speed of switching from high to low level converter outputs | Dec 25, 1991 | Issued |
Array
(
[id] => 2899793
[patent_doc_number] => 05241222
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-31
[patent_title] => 'Dram interface adapter circuit'
[patent_app_type] => 1
[patent_app_number] => 7/810978
[patent_app_country] => US
[patent_app_date] => 1991-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2942
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/241/05241222.pdf
[firstpage_image] =>[orig_patent_app_number] => 810978
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/810978 | Dram interface adapter circuit | Dec 19, 1991 | Issued |
Array
(
[id] => 2938442
[patent_doc_number] => 05220217
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-06-15
[patent_title] => 'Circuit for the generation of a scanning clock in an operational anaylsis device of the serial type for an integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 7/812135
[patent_app_country] => US
[patent_app_date] => 1991-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2285
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/220/05220217.pdf
[firstpage_image] =>[orig_patent_app_number] => 812135
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/812135 | Circuit for the generation of a scanning clock in an operational anaylsis device of the serial type for an integrated circuit | Dec 17, 1991 | Issued |
Array
(
[id] => 2938191
[patent_doc_number] => 05220205
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-06-15
[patent_title] => 'Output circuit of an integrated circuit having immunity to power source fluctuations'
[patent_app_type] => 1
[patent_app_number] => 7/808921
[patent_app_country] => US
[patent_app_date] => 1991-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 5303
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/220/05220205.pdf
[firstpage_image] =>[orig_patent_app_number] => 808921
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/808921 | Output circuit of an integrated circuit having immunity to power source fluctuations | Dec 17, 1991 | Issued |
Array
(
[id] => 2936498
[patent_doc_number] => 05233237
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-03
[patent_title] => 'BICMOS output buffer noise reduction circuit'
[patent_app_type] => 1
[patent_app_number] => 7/803466
[patent_app_country] => US
[patent_app_date] => 1991-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 4833
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 246
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/233/05233237.pdf
[firstpage_image] =>[orig_patent_app_number] => 803466
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/803466 | BICMOS output buffer noise reduction circuit | Dec 5, 1991 | Issued |
Array
(
[id] => 2983988
[patent_doc_number] => 05204554
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-04-20
[patent_title] => 'Partial isolation of power rails for output buffer circuits'
[patent_app_type] => 1
[patent_app_number] => 7/802747
[patent_app_country] => US
[patent_app_date] => 1991-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 3218
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/204/05204554.pdf
[firstpage_image] =>[orig_patent_app_number] => 802747
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/802747 | Partial isolation of power rails for output buffer circuits | Dec 5, 1991 | Issued |