John D Pak

Array ( [id] => 2899695 [patent_doc_number] => 05184034 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-02 [patent_title] => 'State-dependent discharge path circuit' [patent_app_type] => 1 [patent_app_number] => 7/804906 [patent_app_country] => US [patent_app_date] => 1991-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3359 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/184/05184034.pdf [firstpage_image] =>[orig_patent_app_number] => 804906 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2936551 [patent_doc_number] => 05233240 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-03 [patent_title] => 'Semiconductor decoding device comprising an MOS FET for discharging an output terminal' [patent_app_type] => 1 [patent_app_number] => 7/794525 [patent_app_country] => US [patent_app_date] => 1991-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 9417 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 433 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/233/05233240.pdf [firstpage_image] =>[orig_patent_app_number] => 794525 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3054112 [patent_doc_number] => 05287235 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-15 [patent_title] => 'Slider air bearing surface with angled rail configuration' [patent_app_type] => 1 [patent_app_number] => 7/783477 [patent_app_country] => US [patent_app_date] => 1991-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 5494 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/287/05287235.pdf [firstpage_image] =>[orig_patent_app_number] => 783477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2902951 [patent_doc_number] => 05270893 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-14 [patent_title] => 'Specific core structure in a magneto-resistance head' [patent_app_type] => 1 [patent_app_number] => 7/783166 [patent_app_country] => US [patent_app_date] => 1991-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5118 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/270/05270893.pdf [firstpage_image] =>[orig_patent_app_number] => 783166 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2959227 [patent_doc_number] => 05262914 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-16 [patent_title] => 'Magnetoresistive head with enhanced exchange bias field' [patent_app_type] => 1 [patent_app_number] => 7/779221 [patent_app_country] => US [patent_app_date] => 1991-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2323 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/262/05262914.pdf [firstpage_image] =>[orig_patent_app_number] => 779221 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2978146 [patent_doc_number] => 05258884 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-02 [patent_title] => 'Magnetoresistive read transducer containing a titanium and tungsten alloy spacer layer' [patent_app_type] => 1 [patent_app_number] => 7/779419 [patent_app_country] => US [patent_app_date] => 1991-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1979 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/258/05258884.pdf [firstpage_image] =>[orig_patent_app_number] => 779419 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3030696 [patent_doc_number] => 05289330 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-22 [patent_title] => 'Helical read/write head having a cross-cut groove' [patent_app_type] => 1 [patent_app_number] => 7/771043 [patent_app_country] => US [patent_app_date] => 1991-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3015 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/289/05289330.pdf [firstpage_image] =>[orig_patent_app_number] => 771043 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3501053 [patent_doc_number] => 05537277 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'Magnetic head for use in converting a low track density disk to a high track density disk' [patent_app_type] => 1 [patent_app_number] => 7/769857 [patent_app_country] => US [patent_app_date] => 1991-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5057 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/537/05537277.pdf [firstpage_image] =>[orig_patent_app_number] => 769857 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2938260 [patent_doc_number] => 05220209 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-15 [patent_title] => 'Edge rate controlled output buffer circuit with controlled charge storage' [patent_app_type] => 1 [patent_app_number] => 7/767103 [patent_app_country] => US [patent_app_date] => 1991-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6994 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/220/05220209.pdf [firstpage_image] =>[orig_patent_app_number] => 767103 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2937906 [patent_doc_number] => 05189320 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-23 [patent_title] => 'Programmable logic device with multiple shared logic arrays' [patent_app_type] => 1 [patent_app_number] => 7/763921 [patent_app_country] => US [patent_app_date] => 1991-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2641 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/189/05189320.pdf [firstpage_image] =>[orig_patent_app_number] => 763921 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2899679 [patent_doc_number] => 05184033 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-02 [patent_title] => 'Regulated BiCMOS output buffer' [patent_app_type] => 1 [patent_app_number] => 7/763018 [patent_app_country] => US [patent_app_date] => 1991-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 8298 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/184/05184033.pdf [firstpage_image] =>[orig_patent_app_number] => 763018 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3491006 [patent_doc_number] => 05457771 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-10 [patent_title] => 'Integrated circuit with non-volatile, variable resistor, for use in neuronic network' [patent_app_type] => 1 [patent_app_number] => 7/762817 [patent_app_country] => US [patent_app_date] => 1991-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2731 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/457/05457771.pdf [firstpage_image] =>[orig_patent_app_number] => 762817 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2897397 [patent_doc_number] => 05210449 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-11 [patent_title] => 'Edge triggered tri-state output buffer' [patent_app_type] => 1 [patent_app_number] => 7/760622 [patent_app_country] => US [patent_app_date] => 1991-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 2148 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/210/05210449.pdf [firstpage_image] =>[orig_patent_app_number] => 760622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3017077 [patent_doc_number] => 05332932 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-26 [patent_title] => 'Output driver circuit having reduced VSS/VDD voltage fluctuations' [patent_app_type] => 1 [patent_app_number] => 7/760310 [patent_app_country] => US [patent_app_date] => 1991-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4690 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/332/05332932.pdf [firstpage_image] =>[orig_patent_app_number] => 760310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2842752 [patent_doc_number] => 05160860 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-03 [patent_title] => 'Input transition responsive CMOS self-boost circuit' [patent_app_type] => 1 [patent_app_number] => 7/760414 [patent_app_country] => US [patent_app_date] => 1991-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3203 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/160/05160860.pdf [firstpage_image] =>[orig_patent_app_number] => 760414 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2943596 [patent_doc_number] => 05191244 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-02 [patent_title] => 'N-channel pull-up transistor with reduced body effect' [patent_app_type] => 1 [patent_app_number] => 7/760313 [patent_app_country] => US [patent_app_date] => 1991-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3820 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/191/05191244.pdf [firstpage_image] =>[orig_patent_app_number] => 760313 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2959876 [patent_doc_number] => 05243238 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-07 [patent_title] => 'Configurable cellular array' [patent_app_type] => 1 [patent_app_number] => 7/761835 [patent_app_country] => US [patent_app_date] => 1991-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 23 [patent_no_of_words] => 7466 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/243/05243238.pdf [firstpage_image] =>[orig_patent_app_number] => 761835 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2967251 [patent_doc_number] => 05274280 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-28 [patent_title] => 'Semiconductor integrated circuit device having separate supply voltages for the logic stage and output stage' [patent_app_type] => 1 [patent_app_number] => 7/759428 [patent_app_country] => US [patent_app_date] => 1991-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 7219 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/274/05274280.pdf [firstpage_image] =>[orig_patent_app_number] => 759428 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2942520 [patent_doc_number] => 05260610 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-09 [patent_title] => 'Programmable logic element interconnections for programmable logic array integrated circuits' [patent_app_type] => 1 [patent_app_number] => 7/754017 [patent_app_country] => US [patent_app_date] => 1991-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 3418 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/260/05260610.pdf [firstpage_image] =>[orig_patent_app_number] => 754017 [rel_patent_id] =>[rel_patent_doc_number] =>)