Application number | Title of the application | Filing Date | Status |
---|
Array
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[patent_doc_number] => 05698995
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-16
[patent_title] => 'Clock signal generator and integrated circuit including the clock signal generator'
[patent_app_type] => 1
[patent_app_number] => 8/636908
[patent_app_country] => US
[patent_app_date] => 1996-04-22
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[firstpage_image] =>[orig_patent_app_number] => 636908
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/636908 | Clock signal generator and integrated circuit including the clock signal generator | Apr 21, 1996 | Issued |
Array
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[patent_doc_number] => 05760606
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-02
[patent_title] => 'High voltage withstanding circuit and voltage level shifter'
[patent_app_type] => 1
[patent_app_number] => 8/633683
[patent_app_country] => US
[patent_app_date] => 1996-04-17
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Array
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[patent_doc_number] => 05731717
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-24
[patent_title] => 'Logic or memory element based on n-stable phase-locking of single-electron tunneling oscillation, and computer using the same'
[patent_app_type] => 1
[patent_app_number] => 8/628352
[patent_app_country] => US
[patent_app_date] => 1996-04-05
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/628352 | Logic or memory element based on n-stable phase-locking of single-electron tunneling oscillation, and computer using the same | Apr 4, 1996 | Issued |
Array
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[id] => 3905655
[patent_doc_number] => 05751161
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-12
[patent_title] => 'Update scheme for impedance controlled I/O buffers'
[patent_app_type] => 1
[patent_app_number] => 8/626272
[patent_app_country] => US
[patent_app_date] => 1996-04-04
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Array
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[id] => 3737446
[patent_doc_number] => 05694058
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-02
[patent_title] => 'Programmable logic array integrated circuits with improved interconnection conductor utilization'
[patent_app_type] => 1
[patent_app_number] => 8/619072
[patent_app_country] => US
[patent_app_date] => 1996-03-20
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[firstpage_image] =>[orig_patent_app_number] => 619072
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/619072 | Programmable logic array integrated circuits with improved interconnection conductor utilization | Mar 19, 1996 | Issued |
Array
(
[id] => 3728450
[patent_doc_number] => 05682107
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-10-28
[patent_title] => 'FPGA architecture with repeatable tiles including routing matrices and logic matrices'
[patent_app_type] => 1
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/618445 | FPGA architecture with repeatable tiles including routing matrices and logic matrices | Mar 18, 1996 | Issued |
08/608234 | METHOD AND APPARATUS FOR SHARING A FET BETWEEN A PLURALITY OF OPERATIONALLY EXCLUSIVE LOGIC GATES | Feb 27, 1996 | Abandoned |
Array
(
[id] => 3863402
[patent_doc_number] => 05705937
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-01-06
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[patent_app_type] => 1
[patent_app_number] => 8/605924
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 605924
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/605924 | Apparatus for programmable dynamic termination | Feb 22, 1996 | Issued |
Array
(
[id] => 3799158
[patent_doc_number] => 05726591
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-10
[patent_title] => 'MESFET logic device with clamped output drive capacity and low power'
[patent_app_type] => 1
[patent_app_number] => 8/605715
[patent_app_country] => US
[patent_app_date] => 1996-02-22
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 605715
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/605715 | MESFET logic device with clamped output drive capacity and low power | Feb 21, 1996 | Issued |
Array
(
[id] => 3625706
[patent_doc_number] => 05642060
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-24
[patent_title] => 'Clock generator'
[patent_app_type] => 1
[patent_app_number] => 8/604432
[patent_app_country] => US
[patent_app_date] => 1996-02-21
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[firstpage_image] =>[orig_patent_app_number] => 604432
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/604432 | Clock generator | Feb 20, 1996 | Issued |
Array
(
[id] => 3666753
[patent_doc_number] => 05656956
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-12
[patent_title] => 'Logic gate circuit and digital integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/590526
[patent_app_country] => US
[patent_app_date] => 1996-01-24
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[firstpage_image] =>[orig_patent_app_number] => 590526
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/590526 | Logic gate circuit and digital integrated circuit | Jan 23, 1996 | Issued |
08/584997 | PROGRAMMABLE LOGIC DEVICE WITH FIXED AND PROGRAMMABLE MEMORY | Jan 10, 1996 | Abandoned |
Array
(
[id] => 3707496
[patent_doc_number] => 05646549
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-08
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[patent_app_type] => 1
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[firstpage_image] =>[orig_patent_app_number] => 582931
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/582931 | Semiconductor device having an output circuit for transmitting low-voltage differential signals | Jan 3, 1996 | Issued |
Array
(
[id] => 3866954
[patent_doc_number] => 05793225
[patent_country] => US
[patent_kind] => NA
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/581901 | CMOS SONET/ATM receiver suitable for use with pseudo ECL and TTL signaling environments | Jan 1, 1996 | Issued |
Array
(
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[patent_kind] => NA
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/580131 | Method and apparatus for bi-directional bus driver | Dec 27, 1995 | Issued |
Array
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[id] => 3688023
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[patent_kind] => NA
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Array
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[patent_kind] => NA
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/576270 | Full differential data qualification circuit for sensing a logic state | Dec 20, 1995 | Issued |
Array
(
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[patent_kind] => NA
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/573237 | Method and apparatus for implementing an internal tri-state bus within a programmable logic circuit | Dec 14, 1995 | Issued |
Array
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