Search

John D Pak

Examiner (ID: 1394, Phone: (571)272-0620 , Office: P/1616 )

Most Active Art Unit
1616
Art Unit(s)
1209, 1616, 1621, 1699, 2899
Total Applications
2636
Issued Applications
1470
Pending Applications
229
Abandoned Applications
937

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3742620 [patent_doc_number] => 05698995 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Clock signal generator and integrated circuit including the clock signal generator' [patent_app_type] => 1 [patent_app_number] => 8/636908 [patent_app_country] => US [patent_app_date] => 1996-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 7912 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/698/05698995.pdf [firstpage_image] =>[orig_patent_app_number] => 636908 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/636908
Clock signal generator and integrated circuit including the clock signal generator Apr 21, 1996 Issued
Array ( [id] => 3836885 [patent_doc_number] => 05760606 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'High voltage withstanding circuit and voltage level shifter' [patent_app_type] => 1 [patent_app_number] => 8/633683 [patent_app_country] => US [patent_app_date] => 1996-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 6182 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/760/05760606.pdf [firstpage_image] =>[orig_patent_app_number] => 633683 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/633683
High voltage withstanding circuit and voltage level shifter Apr 16, 1996 Issued
Array ( [id] => 3831674 [patent_doc_number] => 05731717 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Logic or memory element based on n-stable phase-locking of single-electron tunneling oscillation, and computer using the same' [patent_app_type] => 1 [patent_app_number] => 8/628352 [patent_app_country] => US [patent_app_date] => 1996-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 41 [patent_no_of_words] => 7646 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/731/05731717.pdf [firstpage_image] =>[orig_patent_app_number] => 628352 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/628352
Logic or memory element based on n-stable phase-locking of single-electron tunneling oscillation, and computer using the same Apr 4, 1996 Issued
Array ( [id] => 3905655 [patent_doc_number] => 05751161 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Update scheme for impedance controlled I/O buffers' [patent_app_type] => 1 [patent_app_number] => 8/626272 [patent_app_country] => US [patent_app_date] => 1996-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3561 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751161.pdf [firstpage_image] =>[orig_patent_app_number] => 626272 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/626272
Update scheme for impedance controlled I/O buffers Apr 3, 1996 Issued
Array ( [id] => 3737446 [patent_doc_number] => 05694058 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Programmable logic array integrated circuits with improved interconnection conductor utilization' [patent_app_type] => 1 [patent_app_number] => 8/619072 [patent_app_country] => US [patent_app_date] => 1996-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2721 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694058.pdf [firstpage_image] =>[orig_patent_app_number] => 619072 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/619072
Programmable logic array integrated circuits with improved interconnection conductor utilization Mar 19, 1996 Issued
Array ( [id] => 3728450 [patent_doc_number] => 05682107 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'FPGA architecture with repeatable tiles including routing matrices and logic matrices' [patent_app_type] => 1 [patent_app_number] => 8/618445 [patent_app_country] => US [patent_app_date] => 1996-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 30 [patent_no_of_words] => 12516 [patent_no_of_claims] => 75 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/682/05682107.pdf [firstpage_image] =>[orig_patent_app_number] => 618445 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/618445
FPGA architecture with repeatable tiles including routing matrices and logic matrices Mar 18, 1996 Issued
08/608234 METHOD AND APPARATUS FOR SHARING A FET BETWEEN A PLURALITY OF OPERATIONALLY EXCLUSIVE LOGIC GATES Feb 27, 1996 Abandoned
Array ( [id] => 3863402 [patent_doc_number] => 05705937 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Apparatus for programmable dynamic termination' [patent_app_type] => 1 [patent_app_number] => 8/605924 [patent_app_country] => US [patent_app_date] => 1996-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2279 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/705/05705937.pdf [firstpage_image] =>[orig_patent_app_number] => 605924 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/605924
Apparatus for programmable dynamic termination Feb 22, 1996 Issued
Array ( [id] => 3799158 [patent_doc_number] => 05726591 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-10 [patent_title] => 'MESFET logic device with clamped output drive capacity and low power' [patent_app_type] => 1 [patent_app_number] => 8/605715 [patent_app_country] => US [patent_app_date] => 1996-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 14544 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/726/05726591.pdf [firstpage_image] =>[orig_patent_app_number] => 605715 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/605715
MESFET logic device with clamped output drive capacity and low power Feb 21, 1996 Issued
Array ( [id] => 3625706 [patent_doc_number] => 05642060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-24 [patent_title] => 'Clock generator' [patent_app_type] => 1 [patent_app_number] => 8/604432 [patent_app_country] => US [patent_app_date] => 1996-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5578 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/642/05642060.pdf [firstpage_image] =>[orig_patent_app_number] => 604432 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/604432
Clock generator Feb 20, 1996 Issued
Array ( [id] => 3666753 [patent_doc_number] => 05656956 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Logic gate circuit and digital integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/590526 [patent_app_country] => US [patent_app_date] => 1996-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 27 [patent_no_of_words] => 18633 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/656/05656956.pdf [firstpage_image] =>[orig_patent_app_number] => 590526 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/590526
Logic gate circuit and digital integrated circuit Jan 23, 1996 Issued
08/584997 PROGRAMMABLE LOGIC DEVICE WITH FIXED AND PROGRAMMABLE MEMORY Jan 10, 1996 Abandoned
Array ( [id] => 3707496 [patent_doc_number] => 05646549 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-08 [patent_title] => 'Semiconductor device having an output circuit for transmitting low-voltage differential signals' [patent_app_type] => 1 [patent_app_number] => 8/582931 [patent_app_country] => US [patent_app_date] => 1996-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 7261 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/646/05646549.pdf [firstpage_image] =>[orig_patent_app_number] => 582931 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/582931
Semiconductor device having an output circuit for transmitting low-voltage differential signals Jan 3, 1996 Issued
Array ( [id] => 3866954 [patent_doc_number] => 05793225 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'CMOS SONET/ATM receiver suitable for use with pseudo ECL and TTL signaling environments' [patent_app_type] => 1 [patent_app_number] => 8/581901 [patent_app_country] => US [patent_app_date] => 1996-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3597 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793225.pdf [firstpage_image] =>[orig_patent_app_number] => 581901 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/581901
CMOS SONET/ATM receiver suitable for use with pseudo ECL and TTL signaling environments Jan 1, 1996 Issued
Array ( [id] => 3792423 [patent_doc_number] => 05736870 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Method and apparatus for bi-directional bus driver' [patent_app_type] => 1 [patent_app_number] => 8/580131 [patent_app_country] => US [patent_app_date] => 1995-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 4525 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/736/05736870.pdf [firstpage_image] =>[orig_patent_app_number] => 580131 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/580131
Method and apparatus for bi-directional bus driver Dec 27, 1995 Issued
Array ( [id] => 3688023 [patent_doc_number] => 05633603 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-27 [patent_title] => 'Data output buffer using pass transistors biased with a reference voltage and a precharged data input' [patent_app_type] => 1 [patent_app_number] => 8/579578 [patent_app_country] => US [patent_app_date] => 1995-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4055 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/633/05633603.pdf [firstpage_image] =>[orig_patent_app_number] => 579578 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/579578
Data output buffer using pass transistors biased with a reference voltage and a precharged data input Dec 25, 1995 Issued
Array ( [id] => 3837792 [patent_doc_number] => 05712581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'Full differential data qualification circuit for sensing a logic state' [patent_app_type] => 1 [patent_app_number] => 8/576270 [patent_app_country] => US [patent_app_date] => 1995-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4631 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/712/05712581.pdf [firstpage_image] =>[orig_patent_app_number] => 576270 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/576270
Full differential data qualification circuit for sensing a logic state Dec 20, 1995 Issued
Array ( [id] => 3722810 [patent_doc_number] => 05617040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-01 [patent_title] => 'Programmable output device with integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/575096 [patent_app_country] => US [patent_app_date] => 1995-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3936 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/617/05617040.pdf [firstpage_image] =>[orig_patent_app_number] => 575096 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/575096
Programmable output device with integrated circuit Dec 18, 1995 Issued
Array ( [id] => 3777734 [patent_doc_number] => 05773994 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Method and apparatus for implementing an internal tri-state bus within a programmable logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/573237 [patent_app_country] => US [patent_app_date] => 1995-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4329 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/773/05773994.pdf [firstpage_image] =>[orig_patent_app_number] => 573237 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/573237
Method and apparatus for implementing an internal tri-state bus within a programmable logic circuit Dec 14, 1995 Issued
Array ( [id] => 3673452 [patent_doc_number] => 05600267 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-04 [patent_title] => 'Apparatus for a programmable CML to CMOS translator for power/speed adjustment' [patent_app_type] => 1 [patent_app_number] => 8/563350 [patent_app_country] => US [patent_app_date] => 1995-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4184 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/600/05600267.pdf [firstpage_image] =>[orig_patent_app_number] => 563350 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/563350
Apparatus for a programmable CML to CMOS translator for power/speed adjustment Nov 27, 1995 Issued
Menu