Search

John D Pak

Examiner (ID: 1394, Phone: (571)272-0620 , Office: P/1616 )

Most Active Art Unit
1616
Art Unit(s)
1209, 1616, 1621, 1699, 2899
Total Applications
2636
Issued Applications
1470
Pending Applications
229
Abandoned Applications
937

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3595939 [patent_doc_number] => 05568060 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-22 [patent_title] => 'Circuit board insertion circuitry for high reliability backplanes' [patent_app_type] => 1 [patent_app_number] => 8/504568 [patent_app_country] => US [patent_app_date] => 1995-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3477 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/568/05568060.pdf [firstpage_image] =>[orig_patent_app_number] => 504568 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/504568
Circuit board insertion circuitry for high reliability backplanes Jul 19, 1995 Issued
Array ( [id] => 3619738 [patent_doc_number] => 05510728 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-23 [patent_title] => 'Multi-finger input buffer with transistor gates capacitively coupled to ground' [patent_app_type] => 1 [patent_app_number] => 8/502464 [patent_app_country] => US [patent_app_date] => 1995-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3387 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/510/05510728.pdf [firstpage_image] =>[orig_patent_app_number] => 502464 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/502464
Multi-finger input buffer with transistor gates capacitively coupled to ground Jul 12, 1995 Issued
Array ( [id] => 3595414 [patent_doc_number] => 05585742 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-17 [patent_title] => 'Bus drivers using skew compensation delay circuits for enabling tristate output buffers' [patent_app_type] => 1 [patent_app_number] => 8/500783 [patent_app_country] => US [patent_app_date] => 1995-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1766 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/585/05585742.pdf [firstpage_image] =>[orig_patent_app_number] => 500783 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/500783
Bus drivers using skew compensation delay circuits for enabling tristate output buffers Jul 10, 1995 Issued
08/500294 SYSTEM COMPRISING FIELD PROGRAMMABLE GATE ARRAY AND INTELLIGENT MEMORY Jul 9, 1995 Abandoned
Array ( [id] => 3654125 [patent_doc_number] => 05684410 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'Preconditioning of output buffers' [patent_app_type] => 1 [patent_app_number] => 8/497794 [patent_app_country] => US [patent_app_date] => 1995-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5275 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/684/05684410.pdf [firstpage_image] =>[orig_patent_app_number] => 497794 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/497794
Preconditioning of output buffers Jul 2, 1995 Issued
Array ( [id] => 3655360 [patent_doc_number] => 05606266 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-25 [patent_title] => 'Programmable logic array integrated circuits with enhanced output routing' [patent_app_type] => 1 [patent_app_number] => 8/497504 [patent_app_country] => US [patent_app_date] => 1995-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5183 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/606/05606266.pdf [firstpage_image] =>[orig_patent_app_number] => 497504 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/497504
Programmable logic array integrated circuits with enhanced output routing Jun 29, 1995 Issued
Array ( [id] => 3664488 [patent_doc_number] => 05592107 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Configurable NAND/NOR element' [patent_app_type] => 1 [patent_app_number] => 8/497491 [patent_app_country] => US [patent_app_date] => 1995-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3412 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/592/05592107.pdf [firstpage_image] =>[orig_patent_app_number] => 497491 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/497491
Configurable NAND/NOR element Jun 29, 1995 Issued
Array ( [id] => 3628027 [patent_doc_number] => 05594364 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'Programmable application specific integrated circuit and logic cell therefor' [patent_app_type] => 1 [patent_app_number] => 8/493981 [patent_app_country] => US [patent_app_date] => 1995-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6731 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/594/05594364.pdf [firstpage_image] =>[orig_patent_app_number] => 493981 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/493981
Programmable application specific integrated circuit and logic cell therefor Jun 22, 1995 Issued
Array ( [id] => 3670050 [patent_doc_number] => 05668483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-16 [patent_title] => 'CMOS buffer having stable threshold voltage' [patent_app_type] => 1 [patent_app_number] => 8/493166 [patent_app_country] => US [patent_app_date] => 1995-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4125 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/668/05668483.pdf [firstpage_image] =>[orig_patent_app_number] => 493166 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/493166
CMOS buffer having stable threshold voltage Jun 20, 1995 Issued
08/490336 SOURCE-COUPLED LOGIC WITH REFERENCE CONTROLLED INPUTS Jun 14, 1995 Abandoned
Array ( [id] => 3543101 [patent_doc_number] => 05495187 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-27 [patent_title] => 'CMOS input with Vcc compensated dynamic threshold' [patent_app_type] => 1 [patent_app_number] => 8/489242 [patent_app_country] => US [patent_app_date] => 1995-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2500 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/495/05495187.pdf [firstpage_image] =>[orig_patent_app_number] => 489242 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/489242
CMOS input with Vcc compensated dynamic threshold Jun 11, 1995 Issued
Array ( [id] => 3639770 [patent_doc_number] => 05610537 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-11 [patent_title] => 'Trinary logic input gate' [patent_app_type] => 1 [patent_app_number] => 8/472583 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 7350 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/610/05610537.pdf [firstpage_image] =>[orig_patent_app_number] => 472583 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/472583
Trinary logic input gate Jun 6, 1995 Issued
Array ( [id] => 3722841 [patent_doc_number] => 05617042 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-01 [patent_title] => 'Multiple array programmable logic device with a plurality of programmable switch matrices' [patent_app_type] => 1 [patent_app_number] => 8/483623 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 33 [patent_no_of_words] => 19217 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/617/05617042.pdf [firstpage_image] =>[orig_patent_app_number] => 483623 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/483623
Multiple array programmable logic device with a plurality of programmable switch matrices Jun 6, 1995 Issued
Array ( [id] => 3497790 [patent_doc_number] => 05537062 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'Glitch-free clock enable circuit' [patent_app_type] => 1 [patent_app_number] => 8/485477 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3648 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/537/05537062.pdf [firstpage_image] =>[orig_patent_app_number] => 485477 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/485477
Glitch-free clock enable circuit Jun 6, 1995 Issued
Array ( [id] => 3730835 [patent_doc_number] => 05701091 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Routing resources for hierarchical FPGA' [patent_app_type] => 1 [patent_app_number] => 8/482339 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 2882 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/701/05701091.pdf [firstpage_image] =>[orig_patent_app_number] => 482339 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/482339
Routing resources for hierarchical FPGA Jun 5, 1995 Issued
Array ( [id] => 3628041 [patent_doc_number] => 05594365 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'Flexible block clock generation circuit for providing clock signals to clocked elements in a multiple array high density programmable logic device' [patent_app_type] => 1 [patent_app_number] => 8/486174 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 33 [patent_no_of_words] => 19889 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/594/05594365.pdf [firstpage_image] =>[orig_patent_app_number] => 486174 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/486174
Flexible block clock generation circuit for providing clock signals to clocked elements in a multiple array high density programmable logic device Jun 5, 1995 Issued
Array ( [id] => 3628651 [patent_doc_number] => 05612631 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-18 [patent_title] => 'An I/O macrocell for a programmable logic device' [patent_app_type] => 1 [patent_app_number] => 8/474629 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 119 [patent_figures_cnt] => 131 [patent_no_of_words] => 30310 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/612/05612631.pdf [firstpage_image] =>[orig_patent_app_number] => 474629 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/474629
An I/O macrocell for a programmable logic device Jun 5, 1995 Issued
Array ( [id] => 3530608 [patent_doc_number] => 05504439 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-02 [patent_title] => 'I/O interface cell for use with optional pad' [patent_app_type] => 1 [patent_app_number] => 8/484064 [patent_app_country] => US [patent_app_date] => 1995-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2637 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/504/05504439.pdf [firstpage_image] =>[orig_patent_app_number] => 484064 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/484064
I/O interface cell for use with optional pad Jun 5, 1995 Issued
Array ( [id] => 3699848 [patent_doc_number] => 05661413 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Processor utilizing a low voltage data circuit and a high voltage controller' [patent_app_type] => 1 [patent_app_number] => 8/461403 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5276 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661413.pdf [firstpage_image] =>[orig_patent_app_number] => 461403 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/461403
Processor utilizing a low voltage data circuit and a high voltage controller Jun 4, 1995 Issued
Array ( [id] => 3700589 [patent_doc_number] => 05619147 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-08 [patent_title] => 'CMOS buffer with controlled slew rate' [patent_app_type] => 1 [patent_app_number] => 8/465153 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4147 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/619/05619147.pdf [firstpage_image] =>[orig_patent_app_number] => 465153 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/465153
CMOS buffer with controlled slew rate Jun 4, 1995 Issued
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