John D Pak

Array ( [id] => 3639575 [patent_doc_number] => 05631578 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-20 [patent_title] => 'Programmable array interconnect network' [patent_app_type] => 1 [patent_app_number] => 8/459579 [patent_app_country] => US [patent_app_date] => 1995-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5479 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/631/05631578.pdf [firstpage_image] =>[orig_patent_app_number] => 459579 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3707454 [patent_doc_number] => 05646546 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-08 [patent_title] => 'Programmable logic cell having configurable gates and multiplexers' [patent_app_type] => 1 [patent_app_number] => 8/460481 [patent_app_country] => US [patent_app_date] => 1995-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 10565 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/646/05646546.pdf [firstpage_image] =>[orig_patent_app_number] => 460481 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3497776 [patent_doc_number] => 05537061 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-16 [patent_title] => 'Semiconductor integrated circuit having signal paths with equal propagation delays' [patent_app_type] => 1 [patent_app_number] => 8/460596 [patent_app_country] => US [patent_app_date] => 1995-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4235 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/537/05537061.pdf [firstpage_image] =>[orig_patent_app_number] => 460596 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3560545 [patent_doc_number] => 05543735 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-06 [patent_title] => 'Method of controlling signal transfer between self-resetting logic circuits' [patent_app_type] => 1 [patent_app_number] => 8/458371 [patent_app_country] => US [patent_app_date] => 1995-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3589 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/543/05543735.pdf [firstpage_image] =>[orig_patent_app_number] => 458371 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3722824 [patent_doc_number] => 05617041 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-01 [patent_title] => 'Method and apparatus for reducing coupling switching noise in interconnect array matrix' [patent_app_type] => 1 [patent_app_number] => 8/459236 [patent_app_country] => US [patent_app_date] => 1995-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4930 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/617/05617041.pdf [firstpage_image] =>[orig_patent_app_number] => 459236 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3535651 [patent_doc_number] => 05583451 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-10 [patent_title] => 'Polarity control circuit which may be used with a ground bounce limiting buffer' [patent_app_type] => 1 [patent_app_number] => 8/453479 [patent_app_country] => US [patent_app_date] => 1995-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6024 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/583/05583451.pdf [firstpage_image] =>[orig_patent_app_number] => 453479 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3654160 [patent_doc_number] => 05640106 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-17 [patent_title] => 'Method and structure for loading data into several IC devices' [patent_app_type] => 1 [patent_app_number] => 8/451781 [patent_app_country] => US [patent_app_date] => 1995-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3157 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/640/05640106.pdf [firstpage_image] =>[orig_patent_app_number] => 451781 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3477604 [patent_doc_number] => 05477166 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-19 [patent_title] => 'Programmable output device with integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/450220 [patent_app_country] => US [patent_app_date] => 1995-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3935 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/477/05477166.pdf [firstpage_image] =>[orig_patent_app_number] => 450220 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3628097 [patent_doc_number] => 05594369 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'Open-drain fet output circuit' [patent_app_type] => 1 [patent_app_number] => 8/449146 [patent_app_country] => US [patent_app_date] => 1995-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 4377 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/594/05594369.pdf [firstpage_image] =>[orig_patent_app_number] => 449146 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3667896 [patent_doc_number] => 05625301 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'Flexible FPGA input/output architecture' [patent_app_type] => 1 [patent_app_number] => 8/444243 [patent_app_country] => US [patent_app_date] => 1995-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7511 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/625/05625301.pdf [firstpage_image] =>[orig_patent_app_number] => 444243 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3728472 [patent_doc_number] => 05682108 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-28 [patent_title] => 'High speed level translator' [patent_app_type] => 1 [patent_app_number] => 8/442725 [patent_app_country] => US [patent_app_date] => 1995-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2905 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/682/05682108.pdf [firstpage_image] =>[orig_patent_app_number] => 442725 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3595274 [patent_doc_number] => 05552940 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-03 [patent_title] => 'Method and apparatus for digital signal recording and/or reproduction' [patent_app_type] => 1 [patent_app_number] => 8/432638 [patent_app_country] => US [patent_app_date] => 1995-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6371 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/552/05552940.pdf [firstpage_image] =>[orig_patent_app_number] => 432638 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3532117 [patent_doc_number] => 05541531 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-30 [patent_title] => 'Switch capacitor interface circuit' [patent_app_type] => 1 [patent_app_number] => 8/432378 [patent_app_country] => US [patent_app_date] => 1995-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4791 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/541/05541531.pdf [firstpage_image] =>[orig_patent_app_number] => 432378 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3514650 [patent_doc_number] => 05587666 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-24 [patent_title] => 'Sense amplifier slew circuitry' [patent_app_type] => 1 [patent_app_number] => 8/428983 [patent_app_country] => US [patent_app_date] => 1995-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1996 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/587/05587666.pdf [firstpage_image] =>[orig_patent_app_number] => 428983 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3502443 [patent_doc_number] => 05532622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-02 [patent_title] => 'Multi-input transition detector with a single delay' [patent_app_type] => 1 [patent_app_number] => 8/427396 [patent_app_country] => US [patent_app_date] => 1995-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1554 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/532/05532622.pdf [firstpage_image] =>[orig_patent_app_number] => 427396 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3525619 [patent_doc_number] => 05530379 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-25 [patent_title] => 'Output buffer circuit that can be shared by a plurality of interfaces and a semiconductor device using the same' [patent_app_type] => 1 [patent_app_number] => 8/427186 [patent_app_country] => US [patent_app_date] => 1995-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 6318 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/530/05530379.pdf [firstpage_image] =>[orig_patent_app_number] => 427186 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3617860 [patent_doc_number] => 05534796 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Self-clocking pipeline register' [patent_app_type] => 1 [patent_app_number] => 8/427076 [patent_app_country] => US [patent_app_date] => 1995-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2039 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/534/05534796.pdf [firstpage_image] =>[orig_patent_app_number] => 427076 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3782450 [patent_doc_number] => 05757206 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Electronic circuit with programmable gradual power consumption control' [patent_app_type] => 1 [patent_app_number] => 8/426442 [patent_app_country] => US [patent_app_date] => 1995-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2501 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/757/05757206.pdf [firstpage_image] =>[orig_patent_app_number] => 426442 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3654209 [patent_doc_number] => 05684416 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'Low voltage bipolar transistor logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/424734 [patent_app_country] => US [patent_app_date] => 1995-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 57 [patent_no_of_words] => 9386 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/684/05684416.pdf [firstpage_image] =>[orig_patent_app_number] => 424734 [rel_patent_id] =>[rel_patent_doc_number] =>)