John D Pak
Examiner (ID: 1394, Phone: (571)272-0620 , Office: P/1616 )
Most Active Art Unit | 1616 |
Art Unit(s) | 1209, 1616, 1621, 1699, 2899 |
Total Applications | 2636 |
Issued Applications | 1470 |
Pending Applications | 229 |
Abandoned Applications | 937 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 3521080
[patent_doc_number] => 05576635
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-19
[patent_title] => 'Output buffer with improved tolerance to overvoltage'
[patent_app_type] => 1
[patent_app_number] => 8/423567
[patent_app_country] => US
[patent_app_date] => 1995-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7360
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/576/05576635.pdf
[firstpage_image] =>[orig_patent_app_number] => 423567
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/423567 | Output buffer with improved tolerance to overvoltage | Apr 16, 1995 | Issued |
Array
(
[id] => 3625720
[patent_doc_number] => 05642061
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-24
[patent_title] => 'Short circuit current free dynamic logic clock timing'
[patent_app_type] => 1
[patent_app_number] => 8/423540
[patent_app_country] => US
[patent_app_date] => 1995-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 8529
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 277
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/642/05642061.pdf
[firstpage_image] =>[orig_patent_app_number] => 423540
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/423540 | Short circuit current free dynamic logic clock timing | Apr 16, 1995 | Issued |
Array
(
[id] => 3594017
[patent_doc_number] => 05517140
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-14
[patent_title] => 'Sample and hold circuit'
[patent_app_type] => 1
[patent_app_number] => 8/421184
[patent_app_country] => US
[patent_app_date] => 1995-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 4462
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/517/05517140.pdf
[firstpage_image] =>[orig_patent_app_number] => 421184
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/421184 | Sample and hold circuit | Apr 12, 1995 | Issued |
Array
(
[id] => 3604123
[patent_doc_number] => 05559452
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-24
[patent_title] => 'N channel output driver with boosted gate voltage'
[patent_app_type] => 1
[patent_app_number] => 8/420487
[patent_app_country] => US
[patent_app_date] => 1995-04-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 21
[patent_no_of_words] => 4844
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/559/05559452.pdf
[firstpage_image] =>[orig_patent_app_number] => 420487
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/420487 | N channel output driver with boosted gate voltage | Apr 11, 1995 | Issued |
Array
(
[id] => 3853878
[patent_doc_number] => 05719505
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-17
[patent_title] => 'Reduced power PLA'
[patent_app_type] => 1
[patent_app_number] => 8/419771
[patent_app_country] => US
[patent_app_date] => 1995-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2830
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/719/05719505.pdf
[firstpage_image] =>[orig_patent_app_number] => 419771
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/419771 | Reduced power PLA | Apr 10, 1995 | Issued |
Array
(
[id] => 3572066
[patent_doc_number] => 05485102
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-16
[patent_title] => 'Programmable logic devices with spare circuits for replacement of defects'
[patent_app_type] => 1
[patent_app_number] => 8/416296
[patent_app_country] => US
[patent_app_date] => 1995-04-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4319
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/485/05485102.pdf
[firstpage_image] =>[orig_patent_app_number] => 416296
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/416296 | Programmable logic devices with spare circuits for replacement of defects | Apr 3, 1995 | Issued |
Array
(
[id] => 3553161
[patent_doc_number] => 05546017
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-13
[patent_title] => 'Hot insertable active SCSI terminator'
[patent_app_type] => 1
[patent_app_number] => 8/409496
[patent_app_country] => US
[patent_app_date] => 1995-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3769
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/546/05546017.pdf
[firstpage_image] =>[orig_patent_app_number] => 409496
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/409496 | Hot insertable active SCSI terminator | Mar 22, 1995 | Issued |
08/410426 | NOISE TOLERANT LOW VOLTAGE BUFFER | Mar 22, 1995 | Abandoned |
Array
(
[id] => 3639608
[patent_doc_number] => 05631580
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-20
[patent_title] => 'BICMOS ECL-CMOS level converter'
[patent_app_type] => 1
[patent_app_number] => 8/405643
[patent_app_country] => US
[patent_app_date] => 1995-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2663
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/631/05631580.pdf
[firstpage_image] =>[orig_patent_app_number] => 405643
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/405643 | BICMOS ECL-CMOS level converter | Mar 16, 1995 | Issued |
Array
(
[id] => 3707636
[patent_doc_number] => 05646559
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-08
[patent_title] => 'Single-electron tunnelling logic device'
[patent_app_type] => 1
[patent_app_number] => 8/403444
[patent_app_country] => US
[patent_app_date] => 1995-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 19
[patent_no_of_words] => 11460
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/646/05646559.pdf
[firstpage_image] =>[orig_patent_app_number] => 403444
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/403444 | Single-electron tunnelling logic device | Mar 14, 1995 | Issued |
Array
(
[id] => 3549590
[patent_doc_number] => 05554942
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-10
[patent_title] => 'Integrated circuit memory having a power supply independent input buffer'
[patent_app_type] => 1
[patent_app_number] => 8/402787
[patent_app_country] => US
[patent_app_date] => 1995-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 5832
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/554/05554942.pdf
[firstpage_image] =>[orig_patent_app_number] => 402787
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/402787 | Integrated circuit memory having a power supply independent input buffer | Mar 12, 1995 | Issued |
Array
(
[id] => 3581174
[patent_doc_number] => 05523706
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-04
[patent_title] => 'High speed, low power macrocell'
[patent_app_type] => 1
[patent_app_number] => 8/401046
[patent_app_country] => US
[patent_app_date] => 1995-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2679
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/523/05523706.pdf
[firstpage_image] =>[orig_patent_app_number] => 401046
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/401046 | High speed, low power macrocell | Mar 7, 1995 | Issued |
Array
(
[id] => 3711793
[patent_doc_number] => 05654648
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-05
[patent_title] => 'Output buffer circuit with low power pre-output drive'
[patent_app_type] => 1
[patent_app_number] => 8/399941
[patent_app_country] => US
[patent_app_date] => 1995-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 2593
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 16
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/654/05654648.pdf
[firstpage_image] =>[orig_patent_app_number] => 399941
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/399941 | Output buffer circuit with low power pre-output drive | Mar 5, 1995 | Issued |
Array
(
[id] => 3629101
[patent_doc_number] => 05602498
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-11
[patent_title] => 'Current switching logic type circuit with small current consumption'
[patent_app_type] => 1
[patent_app_number] => 8/399289
[patent_app_country] => US
[patent_app_date] => 1995-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 20
[patent_no_of_words] => 19449
[patent_no_of_claims] => 7
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[patent_words_short_claim] => 362
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/602/05602498.pdf
[firstpage_image] =>[orig_patent_app_number] => 399289
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/399289 | Current switching logic type circuit with small current consumption | Mar 5, 1995 | Issued |
Array
(
[id] => 3799026
[patent_doc_number] => 05726582
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-10
[patent_title] => 'Control circuit for keeping constant the impedance of a termination network'
[patent_app_type] => 1
[patent_app_number] => 8/393898
[patent_app_country] => US
[patent_app_date] => 1995-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 1819
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/726/05726582.pdf
[firstpage_image] =>[orig_patent_app_number] => 393898
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/393898 | Control circuit for keeping constant the impedance of a termination network | Feb 23, 1995 | Issued |
Array
(
[id] => 3587401
[patent_doc_number] => 05581198
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-03
[patent_title] => 'Shadow DRAM for programmable logic devices'
[patent_app_type] => 1
[patent_app_number] => 8/394092
[patent_app_country] => US
[patent_app_date] => 1995-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 3722
[patent_no_of_claims] => 22
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/581/05581198.pdf
[firstpage_image] =>[orig_patent_app_number] => 394092
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/394092 | Shadow DRAM for programmable logic devices | Feb 23, 1995 | Issued |
08/389783 | OUTPUT BUFFER WITH IMPROVED TOLERANCE TO OVERVOLTAGE | Feb 13, 1995 | Abandoned |
Array
(
[id] => 3516345
[patent_doc_number] => 05563525
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-08
[patent_title] => 'ESD protection device with FET circuit'
[patent_app_type] => 1
[patent_app_number] => 8/387083
[patent_app_country] => US
[patent_app_date] => 1995-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1215
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/563/05563525.pdf
[firstpage_image] =>[orig_patent_app_number] => 387083
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/387083 | ESD protection device with FET circuit | Feb 12, 1995 | Issued |
Array
(
[id] => 3617971
[patent_doc_number] => 05534804
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-09
[patent_title] => 'CMOS power-on reset circuit using hysteresis'
[patent_app_type] => 1
[patent_app_number] => 8/387688
[patent_app_country] => US
[patent_app_date] => 1995-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 6
[patent_no_of_words] => 3062
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/534/05534804.pdf
[firstpage_image] =>[orig_patent_app_number] => 387688
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/387688 | CMOS power-on reset circuit using hysteresis | Feb 12, 1995 | Issued |
Array
(
[id] => 3617757
[patent_doc_number] => 05565790
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-15
[patent_title] => 'ESD protection circuit with field transistor clamp and resistor in the gate circuit of a clamp triggering FET'
[patent_app_type] => 1
[patent_app_number] => 8/387084
[patent_app_country] => US
[patent_app_date] => 1995-02-13
[patent_effective_date] => 0000-00-00
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/565/05565790.pdf
[firstpage_image] =>[orig_patent_app_number] => 387084
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/387084 | ESD protection circuit with field transistor clamp and resistor in the gate circuit of a clamp triggering FET | Feb 12, 1995 | Issued |