Application number | Title of the application | Filing Date | Status |
---|
Array
(
[id] => 3597738
[patent_doc_number] => 05521531
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-28
[patent_title] => 'CMOS bidirectional transceiver/translator operating between two power supplies of different voltages'
[patent_app_type] => 1
[patent_app_number] => 8/354796
[patent_app_country] => US
[patent_app_date] => 1994-12-12
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[pdf_file] => patents/05/521/05521531.pdf
[firstpage_image] =>[orig_patent_app_number] => 354796
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/354796 | CMOS bidirectional transceiver/translator operating between two power supplies of different voltages | Dec 11, 1994 | Issued |
Array
(
[id] => 3736638
[patent_doc_number] => 05635857
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-03
[patent_title] => 'IC chip using a common multiplexor logic element for performing logic operations'
[patent_app_type] => 1
[patent_app_number] => 8/351909
[patent_app_country] => US
[patent_app_date] => 1994-12-08
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 351909
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/351909 | IC chip using a common multiplexor logic element for performing logic operations | Dec 7, 1994 | Issued |
Array
(
[id] => 3562893
[patent_doc_number] => 05502407
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-26
[patent_title] => 'Low-power-dissipation CMOS circuits'
[patent_app_type] => 1
[patent_app_number] => 8/348388
[patent_app_country] => US
[patent_app_date] => 1994-12-02
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/502/05502407.pdf
[firstpage_image] =>[orig_patent_app_number] => 348388
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/348388 | Low-power-dissipation CMOS circuits | Dec 1, 1994 | Issued |
Array
(
[id] => 3576915
[patent_doc_number] => 05539327
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-23
[patent_title] => 'Protection circuit which prevents avalanche breakdown in a fet by having a floating substrate and a voltage controlled gate'
[patent_app_type] => 1
[patent_app_number] => 8/353383
[patent_app_country] => US
[patent_app_date] => 1994-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 2546
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[pdf_file] => patents/05/539/05539327.pdf
[firstpage_image] =>[orig_patent_app_number] => 353383
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/353383 | Protection circuit which prevents avalanche breakdown in a fet by having a floating substrate and a voltage controlled gate | Dec 1, 1994 | Issued |
Array
(
[id] => 3543020
[patent_doc_number] => 05495181
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-27
[patent_title] => 'Integrated circuit facilitating simultaneous programming of multiple antifuses'
[patent_app_type] => 1
[patent_app_number] => 8/349093
[patent_app_country] => US
[patent_app_date] => 1994-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
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[patent_no_of_words] => 2862
[patent_no_of_claims] => 22
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/495/05495181.pdf
[firstpage_image] =>[orig_patent_app_number] => 349093
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/349093 | Integrated circuit facilitating simultaneous programming of multiple antifuses | Nov 30, 1994 | Issued |
Array
(
[id] => 3522808
[patent_doc_number] => 05506517
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-09
[patent_title] => 'Output enable structure and method for a programmable logic device'
[patent_app_type] => 1
[patent_app_number] => 8/342675
[patent_app_country] => US
[patent_app_date] => 1994-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
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[patent_no_of_words] => 3798
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[pdf_file] => patents/05/506/05506517.pdf
[firstpage_image] =>[orig_patent_app_number] => 342675
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/342675 | Output enable structure and method for a programmable logic device | Nov 20, 1994 | Issued |
Array
(
[id] => 3488317
[patent_doc_number] => 05446399
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-29
[patent_title] => 'Method and structure for a fault-free input configuration control mechanism'
[patent_app_type] => 1
[patent_app_number] => 8/342183
[patent_app_country] => US
[patent_app_date] => 1994-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 1794
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/446/05446399.pdf
[firstpage_image] =>[orig_patent_app_number] => 342183
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/342183 | Method and structure for a fault-free input configuration control mechanism | Nov 17, 1994 | Issued |
Array
(
[id] => 3596028
[patent_doc_number] => 05568066
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-22
[patent_title] => 'Sense amplifier and or gate for a high density programmable logic device'
[patent_app_type] => 1
[patent_app_number] => 8/341432
[patent_app_country] => US
[patent_app_date] => 1994-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 7037
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/568/05568066.pdf
[firstpage_image] =>[orig_patent_app_number] => 341432
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/341432 | Sense amplifier and or gate for a high density programmable logic device | Nov 16, 1994 | Issued |
Array
(
[id] => 3700819
[patent_doc_number] => 05596287
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-21
[patent_title] => 'Programmable logic module for data path applications'
[patent_app_type] => 1
[patent_app_number] => 8/343890
[patent_app_country] => US
[patent_app_date] => 1994-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2119
[patent_no_of_claims] => 7
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/596/05596287.pdf
[firstpage_image] =>[orig_patent_app_number] => 343890
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/343890 | Programmable logic module for data path applications | Nov 15, 1994 | Issued |
Array
(
[id] => 3434286
[patent_doc_number] => 05463328
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-10-31
[patent_title] => 'Expanded programmable logic architecture'
[patent_app_type] => 1
[patent_app_number] => 8/337579
[patent_app_country] => US
[patent_app_date] => 1994-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 3194
[patent_no_of_claims] => 22
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/463/05463328.pdf
[firstpage_image] =>[orig_patent_app_number] => 337579
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/337579 | Expanded programmable logic architecture | Nov 9, 1994 | Issued |
08/334879 | PROGRAMMABLE LOGIC DEVICE | Nov 3, 1994 | Abandoned |
Array
(
[id] => 3653231
[patent_doc_number] => 05638009
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-10
[patent_title] => 'Three conductor asynchronous signaling'
[patent_app_type] => 1
[patent_app_number] => 8/333554
[patent_app_country] => US
[patent_app_date] => 1994-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/638/05638009.pdf
[firstpage_image] =>[orig_patent_app_number] => 333554
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/333554 | Three conductor asynchronous signaling | Nov 1, 1994 | Issued |
Array
(
[id] => 3521281
[patent_doc_number] => 05486774
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-23
[patent_title] => 'CMOS logic circuits having low and high-threshold voltage transistors'
[patent_app_type] => 1
[patent_app_number] => 8/333235
[patent_app_country] => US
[patent_app_date] => 1994-11-02
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/486/05486774.pdf
[firstpage_image] =>[orig_patent_app_number] => 333235
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/333235 | CMOS logic circuits having low and high-threshold voltage transistors | Nov 1, 1994 | Issued |
Array
(
[id] => 3448107
[patent_doc_number] => 05467032
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-14
[patent_title] => 'Word line driver circuit for a semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/332794
[patent_app_country] => US
[patent_app_date] => 1994-11-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/05/467/05467032.pdf
[firstpage_image] =>[orig_patent_app_number] => 332794
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/332794 | Word line driver circuit for a semiconductor memory device | Nov 1, 1994 | Issued |
08/333131 | PROGRAMMABLE MULTIPLEXING INPUT/OUTPUT PORT | Oct 31, 1994 | Abandoned |
Array
(
[id] => 3596982
[patent_doc_number] => 05488325
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-30
[patent_title] => 'Timing generator intended for semiconductor testing apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/324684
[patent_app_country] => US
[patent_app_date] => 1994-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/488/05488325.pdf
[firstpage_image] =>[orig_patent_app_number] => 324684
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/324684 | Timing generator intended for semiconductor testing apparatus | Oct 17, 1994 | Issued |
Array
(
[id] => 3462819
[patent_doc_number] => 05473266
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-05
[patent_title] => 'Programmable logic device having fast programmable logic array blocks and a central global interconnect array'
[patent_app_type] => 1
[patent_app_number] => 8/324860
[patent_app_country] => US
[patent_app_date] => 1994-10-18
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/473/05473266.pdf
[firstpage_image] =>[orig_patent_app_number] => 324860
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/324860 | Programmable logic device having fast programmable logic array blocks and a central global interconnect array | Oct 17, 1994 | Issued |
Array
(
[id] => 3561814
[patent_doc_number] => 05500611
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-19
[patent_title] => 'Integrated circuit with input/output pad having pullup or pulldown'
[patent_app_type] => 1
[patent_app_number] => 8/316178
[patent_app_country] => US
[patent_app_date] => 1994-09-30
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/500/05500611.pdf
[firstpage_image] =>[orig_patent_app_number] => 316178
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/316178 | Integrated circuit with input/output pad having pullup or pulldown | Sep 29, 1994 | Issued |
Array
(
[id] => 3734217
[patent_doc_number] => 05670893
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-23
[patent_title] => 'BiCMOS logic circuit with bipolar base clamping'
[patent_app_type] => 1
[patent_app_number] => 8/312396
[patent_app_country] => US
[patent_app_date] => 1994-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/05/670/05670893.pdf
[firstpage_image] =>[orig_patent_app_number] => 312396
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/312396 | BiCMOS logic circuit with bipolar base clamping | Sep 25, 1994 | Issued |
08/311793 | PROGRAMMABLE LOGIC DEVICE ARCHITECTURE | Sep 25, 1994 | Abandoned |