
John E. Barlow Jr.
Supervisory Patent Examiner (ID: 10238, Phone: (571)272-2269 , Office: P/2800 )
| Most Active Art Unit | 2108 |
| Art Unit(s) | 2105, 2600, 2800, 2863, 2108, 2853, 2857 |
| Total Applications | 691 |
| Issued Applications | 547 |
| Pending Applications | 31 |
| Abandoned Applications | 124 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17963697
[patent_doc_number] => 20220344278
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-27
[patent_title] => SCRIBE STRUCTURE FOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/237992
[patent_app_country] => US
[patent_app_date] => 2021-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8481
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17237992
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/237992 | Scribe structure for memory device | Apr 21, 2021 | Issued |
Array
(
[id] => 17011164
[patent_doc_number] => 20210242325
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-05
[patent_title] => GATE ELECTRODE HAVING A CAPPING LAYER
[patent_app_type] => utility
[patent_app_number] => 17/236338
[patent_app_country] => US
[patent_app_date] => 2021-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5303
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17236338
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/236338 | GATE ELECTRODE HAVING A CAPPING LAYER | Apr 20, 2021 | Pending |
Array
(
[id] => 17174153
[patent_doc_number] => 20210327824
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-21
[patent_title] => SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/235055
[patent_app_country] => US
[patent_app_date] => 2021-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5404
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17235055
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/235055 | Semiconductor package and method for manufacturing the same | Apr 19, 2021 | Issued |
Array
(
[id] => 17026527
[patent_doc_number] => 20210250399
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-12
[patent_title] => SURFACING SHARING ATTRIBUTES OF A LINK PROXIMATE A BROWSER ADDRESS BAR
[patent_app_type] => utility
[patent_app_number] => 17/235458
[patent_app_country] => US
[patent_app_date] => 2021-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7562
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17235458
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/235458 | Surfacing sharing attributes of a link proximate a browser address bar | Apr 19, 2021 | Issued |
Array
(
[id] => 17600546
[patent_doc_number] => 20220150121
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-12
[patent_title] => PROVISIONING RESOURCES FOR A DATACENTER ON A CLOUD PLATFORM BASED ON A PLATFORM INDEPENDENT DECLARATIVE SPECIFICATION
[patent_app_type] => utility
[patent_app_number] => 17/234605
[patent_app_country] => US
[patent_app_date] => 2021-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9889
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17234605
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/234605 | Declarative language and compiler for provisioning and deploying data centers on cloud platforms | Apr 18, 2021 | Issued |
Array
(
[id] => 17949352
[patent_doc_number] => 20220336371
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-20
[patent_title] => SEMICONDUCTOR DEVICE PACKAGING WARPAGE CONTROL
[patent_app_type] => utility
[patent_app_number] => 17/230098
[patent_app_country] => US
[patent_app_date] => 2021-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6446
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17230098
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/230098 | Semiconductor device packaging warpage control | Apr 13, 2021 | Issued |
Array
(
[id] => 17949354
[patent_doc_number] => 20220336373
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-20
[patent_title] => SCRIBE STRUCTURE FOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/230827
[patent_app_country] => US
[patent_app_date] => 2021-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8320
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17230827
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/230827 | Scribe structure for memory device | Apr 13, 2021 | Issued |
Array
(
[id] => 17271367
[patent_doc_number] => 11196807
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-12-07
[patent_title] => Data transmission system with network service decentralization and method thereof
[patent_app_type] => utility
[patent_app_number] => 17/229871
[patent_app_country] => US
[patent_app_date] => 2021-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2820
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 252
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17229871
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/229871 | Data transmission system with network service decentralization and method thereof | Apr 13, 2021 | Issued |
Array
(
[id] => 17949353
[patent_doc_number] => 20220336372
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-20
[patent_title] => SCRIBE STRUCTURE FOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/230772
[patent_app_country] => US
[patent_app_date] => 2021-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9331
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17230772
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/230772 | Scribe structure for memory device | Apr 13, 2021 | Issued |
Array
(
[id] => 18465085
[patent_doc_number] => 11689389
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2023-06-27
[patent_title] => Onboarding a VNF which includes a VNFC composed of manageable software elements
[patent_app_type] => utility
[patent_app_number] => 17/229853
[patent_app_country] => US
[patent_app_date] => 2021-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8630
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17229853
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/229853 | Onboarding a VNF which includes a VNFC composed of manageable software elements | Apr 12, 2021 | Issued |
Array
(
[id] => 17855174
[patent_doc_number] => 20220285217
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-08
[patent_title] => WAFER THINNING METHOD
[patent_app_type] => utility
[patent_app_number] => 17/215417
[patent_app_country] => US
[patent_app_date] => 2021-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 1849
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17215417
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/215417 | WAFER THINNING METHOD | Mar 28, 2021 | Abandoned |
Array
(
[id] => 17431763
[patent_doc_number] => 20220059472
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-24
[patent_title] => SEMICONDUCTOR SUBSTRATE AND METHOD OF SAWING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/216279
[patent_app_country] => US
[patent_app_date] => 2021-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4746
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 52
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17216279
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/216279 | Semiconductor substrate and method of sawing the same | Mar 28, 2021 | Issued |
Array
(
[id] => 17901115
[patent_doc_number] => 20220310777
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-29
[patent_title] => INTEGRATED CIRCUIT PACKAGE REDISTRIBUTION LAYERS WITH METAL-INSULATOR-METAL (MIM) CAPACITORS
[patent_app_type] => utility
[patent_app_number] => 17/213551
[patent_app_country] => US
[patent_app_date] => 2021-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9708
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -20
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213551
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/213551 | Integrated circuit package redistribution layers with metal-insulator-metal (MIM) capacitors | Mar 25, 2021 | Issued |
Array
(
[id] => 18796989
[patent_doc_number] => 11830824
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-11-28
[patent_title] => Edge protection on semiconductor substrates
[patent_app_type] => utility
[patent_app_number] => 17/214411
[patent_app_country] => US
[patent_app_date] => 2021-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 15
[patent_no_of_words] => 7640
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214411
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/214411 | Edge protection on semiconductor substrates | Mar 25, 2021 | Issued |
Array
(
[id] => 17730732
[patent_doc_number] => 11387133
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-12
[patent_title] => Wafer processing method
[patent_app_type] => utility
[patent_app_number] => 17/211186
[patent_app_country] => US
[patent_app_date] => 2021-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 4763
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 240
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17211186
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/211186 | Wafer processing method | Mar 23, 2021 | Issued |
Array
(
[id] => 17772337
[patent_doc_number] => 11404288
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-08-02
[patent_title] => Semiconductor device packaging warpage control
[patent_app_type] => utility
[patent_app_number] => 17/209710
[patent_app_country] => US
[patent_app_date] => 2021-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 5074
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17209710
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/209710 | Semiconductor device packaging warpage control | Mar 22, 2021 | Issued |
Array
(
[id] => 17196878
[patent_doc_number] => 11165655
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-11-02
[patent_title] => System for optimizing enterprise network relations
[patent_app_type] => utility
[patent_app_number] => 17/208758
[patent_app_country] => US
[patent_app_date] => 2021-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 9884
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17208758
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/208758 | System for optimizing enterprise network relations | Mar 21, 2021 | Issued |
Array
(
[id] => 18263108
[patent_doc_number] => 11610817
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-03-21
[patent_title] => Method of processing a semiconductor wafer, semiconductor wafer, and semiconductor die produced from a semiconductor wafer
[patent_app_type] => utility
[patent_app_number] => 17/206782
[patent_app_country] => US
[patent_app_date] => 2021-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6256
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17206782
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/206782 | Method of processing a semiconductor wafer, semiconductor wafer, and semiconductor die produced from a semiconductor wafer | Mar 18, 2021 | Issued |
Array
(
[id] => 17886564
[patent_doc_number] => 20220302042
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-22
[patent_title] => PLATED PILLAR DIES HAVING INTEGRATED ELECTROMAGNETIC SHIELD LAYERS
[patent_app_type] => utility
[patent_app_number] => 17/207022
[patent_app_country] => US
[patent_app_date] => 2021-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9991
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17207022
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/207022 | Plated pillar dies having integrated electromagnetic shield layers | Mar 18, 2021 | Issued |
Array
(
[id] => 18219500
[patent_doc_number] => 11594449
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-28
[patent_title] => Method of making a semiconductor structure
[patent_app_type] => utility
[patent_app_number] => 17/207152
[patent_app_country] => US
[patent_app_date] => 2021-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6297
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17207152
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/207152 | Method of making a semiconductor structure | Mar 18, 2021 | Issued |