Search

John E. Barlow Jr.

Supervisory Patent Examiner (ID: 10238, Phone: (571)272-2269 , Office: P/2800 )

Most Active Art Unit
2108
Art Unit(s)
2105, 2600, 2800, 2863, 2108, 2853, 2857
Total Applications
691
Issued Applications
547
Pending Applications
31
Abandoned Applications
124

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17333204 [patent_doc_number] => 11223678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Establishing paths between servers in a copy environment for different copy relationships between the servers [patent_app_type] => utility [patent_app_number] => 17/095736 [patent_app_country] => US [patent_app_date] => 2020-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 9045 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17095736 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/095736
Establishing paths between servers in a copy environment for different copy relationships between the servers Nov 10, 2020 Issued
Array ( [id] => 16858335 [patent_doc_number] => 20210159080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => WAFER PROCESSING METHOD [patent_app_type] => utility [patent_app_number] => 17/095050 [patent_app_country] => US [patent_app_date] => 2020-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6448 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 334 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17095050 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/095050
Wafer processing method Nov 10, 2020 Issued
Array ( [id] => 17382141 [patent_doc_number] => 11240181 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-01 [patent_title] => Artificial intelligence assisted service provisioning and modification for delivering message-based services [patent_app_type] => utility [patent_app_number] => 17/093596 [patent_app_country] => US [patent_app_date] => 2020-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 28883 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17093596 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/093596
Artificial intelligence assisted service provisioning and modification for delivering message-based services Nov 8, 2020 Issued
Array ( [id] => 16846828 [patent_doc_number] => 11018938 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-05-25 [patent_title] => Auditing metadata representation of a cloud-computing platform based datacenter [patent_app_type] => utility [patent_app_number] => 17/092020 [patent_app_country] => US [patent_app_date] => 2020-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9889 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17092020 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/092020
Auditing metadata representation of a cloud-computing platform based datacenter Nov 5, 2020 Issued
Array ( [id] => 18338178 [patent_doc_number] => 20230130127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => METHOD FOR MANUFACTURING A FUNCTIONAL CHIP SUITABLE FOR BEING ASSEMBLED TO WIRE ELEMENTS [patent_app_type] => utility [patent_app_number] => 17/756325 [patent_app_country] => US [patent_app_date] => 2020-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17756325 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/756325
METHOD FOR MANUFACTURING A FUNCTIONAL CHIP SUITABLE FOR BEING ASSEMBLED TO WIRE ELEMENTS Nov 4, 2020 Abandoned
Array ( [id] => 16631661 [patent_doc_number] => 20210050314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-18 [patent_title] => PAD STRUCTURE AND MANUFACTURING METHOD THEREOF IN SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/088324 [patent_app_country] => US [patent_app_date] => 2020-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6267 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17088324 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/088324
Pad structure and manufacturing method thereof in semiconductor device Nov 2, 2020 Issued
Array ( [id] => 17582916 [patent_doc_number] => 20220139771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/085327 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6390 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085327 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/085327
Semiconductor structure and method for forming the same Oct 29, 2020 Issued
Array ( [id] => 18951007 [patent_doc_number] => 11894313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Substrate processing and packaging [patent_app_type] => utility [patent_app_number] => 17/081611 [patent_app_country] => US [patent_app_date] => 2020-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 9805 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17081611 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/081611
Substrate processing and packaging Oct 26, 2020 Issued
Array ( [id] => 16797011 [patent_doc_number] => 20210126829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => METHODS AND SYSTEMS FOR DETERMINING ICN CAPABILITY OF A NODE/SERVER [patent_app_type] => utility [patent_app_number] => 17/079292 [patent_app_country] => US [patent_app_date] => 2020-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10723 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17079292 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/079292
Methods and systems for determining ICN capability of a node/server Oct 22, 2020 Issued
Array ( [id] => 16624942 [patent_doc_number] => 20210043595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => ELECTRONIC DEVICE INCLUDING FIRST SUBSTRATE HAVING FIRST AND SECOND SURFACES OPPOSITE FROM EACH OTHER, SECOND SUBSTRATE FACING FIRST SURFACE, AND DRIVE CIRCUIT FACING SECOND SURFACE [patent_app_type] => utility [patent_app_number] => 17/078787 [patent_app_country] => US [patent_app_date] => 2020-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12734 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17078787 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/078787
Electronic device including first substrate having first and second surfaces opposite from each other, second substrate facing first surface, and drive circuit facing second surface Oct 22, 2020 Issued
Array ( [id] => 19401201 [patent_doc_number] => 12075612 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-27 [patent_title] => Semiconductor structure and method for forming the same, and memory and method for forming the same [patent_app_type] => utility [patent_app_number] => 17/426503 [patent_app_country] => US [patent_app_date] => 2020-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 28 [patent_no_of_words] => 7683 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17426503 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/426503
Semiconductor structure and method for forming the same, and memory and method for forming the same Oct 19, 2020 Issued
Array ( [id] => 18190676 [patent_doc_number] => 11581278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Semiconductor device and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/074267 [patent_app_country] => US [patent_app_date] => 2020-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 54 [patent_no_of_words] => 7292 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17074267 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/074267
Semiconductor device and method of forming the same Oct 18, 2020 Issued
Array ( [id] => 18249002 [patent_doc_number] => 11605599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-14 [patent_title] => Semiconductor device having a thin semiconductor die [patent_app_type] => utility [patent_app_number] => 17/071022 [patent_app_country] => US [patent_app_date] => 2020-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 6359 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17071022 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/071022
Semiconductor device having a thin semiconductor die Oct 14, 2020 Issued
Array ( [id] => 18520767 [patent_doc_number] => 11710661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-25 [patent_title] => Semiconductor packages and methods of packaging semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/072006 [patent_app_country] => US [patent_app_date] => 2020-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 10258 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17072006 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/072006
Semiconductor packages and methods of packaging semiconductor devices Oct 14, 2020 Issued
Array ( [id] => 18751496 [patent_doc_number] => 11810817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-07 [patent_title] => In-situ CMP self-assembled monolayer for enhancing metal-dielectric adhesion and preventing metal diffusion [patent_app_type] => utility [patent_app_number] => 17/070853 [patent_app_country] => US [patent_app_date] => 2020-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5401 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17070853 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/070853
In-situ CMP self-assembled monolayer for enhancing metal-dielectric adhesion and preventing metal diffusion Oct 13, 2020 Issued
Array ( [id] => 16625185 [patent_doc_number] => 20210043838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => DOPANT-MODULATED ETCHING FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/069380 [patent_app_country] => US [patent_app_date] => 2020-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17069380 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/069380
Dopant-modulated etching for memory devices Oct 12, 2020 Issued
Array ( [id] => 17535422 [patent_doc_number] => 20220114031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => DETERMINING A DEPLOYMENT SCHEDULE FOR OPERATIONS PERFORMED ON DEVICES USING DEVICE DEPENDENCIES AND PREDICTED WORKLOADS [patent_app_type] => utility [patent_app_number] => 17/066647 [patent_app_country] => US [patent_app_date] => 2020-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6905 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17066647 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/066647
Determining a deployment schedule for operations performed on devices using device dependencies and predicted workloads Oct 8, 2020 Issued
Array ( [id] => 17590679 [patent_doc_number] => 11328956 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Wafer processing method [patent_app_type] => utility [patent_app_number] => 17/066658 [patent_app_country] => US [patent_app_date] => 2020-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3341 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17066658 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/066658
Wafer processing method Oct 8, 2020 Issued
Array ( [id] => 17700218 [patent_doc_number] => 11373952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Deep trench protection [patent_app_type] => utility [patent_app_number] => 17/065979 [patent_app_country] => US [patent_app_date] => 2020-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5518 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17065979 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/065979
Deep trench protection Oct 7, 2020 Issued
Array ( [id] => 18277080 [patent_doc_number] => 11616028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-28 [patent_title] => Semiconductor devices having crack-inhibiting structures [patent_app_type] => utility [patent_app_number] => 17/062922 [patent_app_country] => US [patent_app_date] => 2020-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6002 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17062922 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/062922
Semiconductor devices having crack-inhibiting structures Oct 4, 2020 Issued
Menu