Search

John E. Barlow Jr.

Supervisory Patent Examiner (ID: 10238, Phone: (571)272-2269 , Office: P/2800 )

Most Active Art Unit
2108
Art Unit(s)
2105, 2600, 2800, 2863, 2108, 2853, 2857
Total Applications
691
Issued Applications
547
Pending Applications
31
Abandoned Applications
124

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19957315 [patent_doc_number] => 12327732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-10 [patent_title] => Method to improve profile control during selective etching of silicon nitride spacers [patent_app_type] => utility [patent_app_number] => 18/383667 [patent_app_country] => US [patent_app_date] => 2023-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5500 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18383667 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/383667
Method to improve profile control during selective etching of silicon nitride spacers Oct 24, 2023 Issued
Array ( [id] => 19995550 [patent_doc_number] => 20250133772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => BOTTOM CHANNEL TRENCH ISOLATED GATE ALL AROUND (GAA) FIELD EFFECT TRANSISTOR (FET) [patent_app_type] => utility [patent_app_number] => 18/493634 [patent_app_country] => US [patent_app_date] => 2023-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3300 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18493634 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/493634
BOTTOM CHANNEL TRENCH ISOLATED GATE ALL AROUND (GAA) FIELD EFFECT TRANSISTOR (FET) Oct 23, 2023 Pending
Array ( [id] => 18943550 [patent_doc_number] => 20240038689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => Structure and Method for Sealing a Silicon IC [patent_app_type] => utility [patent_app_number] => 18/485709 [patent_app_country] => US [patent_app_date] => 2023-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6911 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18485709 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/485709
Structure and method for sealing a silicon IC Oct 11, 2023 Issued
Array ( [id] => 19277348 [patent_doc_number] => 12027480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-02 [patent_title] => Semiconductor device with wire bond and method for preparing the same [patent_app_type] => utility [patent_app_number] => 18/378885 [patent_app_country] => US [patent_app_date] => 2023-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7087 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18378885 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/378885
Semiconductor device with wire bond and method for preparing the same Oct 10, 2023 Issued
Array ( [id] => 19131000 [patent_doc_number] => 20240136353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => RC-IGBT AND MANUFACTURING METHOD OF RC-IGBT [patent_app_type] => utility [patent_app_number] => 18/483826 [patent_app_country] => US [patent_app_date] => 2023-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18483826 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/483826
RC-IGBT AND MANUFACTURING METHOD OF RC-IGBT Oct 9, 2023 Pending
Array ( [id] => 19131000 [patent_doc_number] => 20240136353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-25 [patent_title] => RC-IGBT AND MANUFACTURING METHOD OF RC-IGBT [patent_app_type] => utility [patent_app_number] => 18/483826 [patent_app_country] => US [patent_app_date] => 2023-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7081 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18483826 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/483826
RC-IGBT AND MANUFACTURING METHOD OF RC-IGBT Oct 8, 2023 Pending
Array ( [id] => 18943613 [patent_doc_number] => 20240038752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => PACKAGE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/481975 [patent_app_country] => US [patent_app_date] => 2023-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6766 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18481975 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/481975
Package structure Oct 4, 2023 Issued
Array ( [id] => 18961283 [patent_doc_number] => 20240049610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => DOPANT-MODULATED ETCHING FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/374925 [patent_app_country] => US [patent_app_date] => 2023-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14259 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18374925 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/374925
Dopant-modulated etching for memory devices Sep 28, 2023 Issued
Array ( [id] => 19057010 [patent_doc_number] => 20240098979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/369957 [patent_app_country] => US [patent_app_date] => 2023-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8467 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18369957 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/369957
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME Sep 18, 2023 Pending
Array ( [id] => 19634653 [patent_doc_number] => 20240413102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => FORMING SHALLOW TRENCH FOR DICING AND STRUCTURES THEREOF [patent_app_type] => utility [patent_app_number] => 18/462499 [patent_app_country] => US [patent_app_date] => 2023-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18462499 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/462499
FORMING SHALLOW TRENCH FOR DICING AND STRUCTURES THEREOF Sep 6, 2023 Pending
Array ( [id] => 19176130 [patent_doc_number] => 20240162104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE, AND SEMICONDUCTOR CHIP MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 18/462010 [patent_app_country] => US [patent_app_date] => 2023-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9649 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18462010 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/462010
SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE, AND SEMICONDUCTOR CHIP MANUFACTURING METHOD Sep 5, 2023 Pending
Array ( [id] => 19071215 [patent_doc_number] => 20240105641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => CORRECTION OF GLOBAL CURVATURE DURING STRESS MANAGEMENT [patent_app_type] => utility [patent_app_number] => 18/242812 [patent_app_country] => US [patent_app_date] => 2023-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4255 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18242812 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/242812
CORRECTION OF GLOBAL CURVATURE DURING STRESS MANAGEMENT Sep 5, 2023 Pending
Array ( [id] => 19821139 [patent_doc_number] => 20250079346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => STRESS REDUCTION STRUCTURES FOR A SEMICONDUCTOR DIE IN A COMPOSITE PACKAGE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/460658 [patent_app_country] => US [patent_app_date] => 2023-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13909 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18460658 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/460658
STRESS REDUCTION STRUCTURES FOR A SEMICONDUCTOR DIE IN A COMPOSITE PACKAGE AND METHODS OF FORMING THE SAME Sep 3, 2023 Pending
Array ( [id] => 20416834 [patent_doc_number] => 12500128 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Four-terminal resistance testing structure [patent_app_type] => utility [patent_app_number] => 18/239844 [patent_app_country] => US [patent_app_date] => 2023-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 0 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18239844 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/239844
Four-terminal resistance testing structure Aug 29, 2023 Issued
Array ( [id] => 19559998 [patent_doc_number] => 20240371790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/458633 [patent_app_country] => US [patent_app_date] => 2023-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5752 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18458633 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/458633
SEMICONDUCTOR DEVICE AND METHOD FORMING THE SAME Aug 29, 2023 Pending
Array ( [id] => 19007709 [patent_doc_number] => 20240071780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREFOR [patent_app_type] => utility [patent_app_number] => 18/456636 [patent_app_country] => US [patent_app_date] => 2023-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18456636 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/456636
ELECTRONIC PACKAGE AND MANUFACTURING METHOD THEREFOR Aug 27, 2023 Pending
Array ( [id] => 19146323 [patent_doc_number] => 20240145353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE, SEMICONDUCTOR DEVICE, AND VEHICLE [patent_app_type] => utility [patent_app_number] => 18/456647 [patent_app_country] => US [patent_app_date] => 2023-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13271 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18456647 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/456647
SEMICONDUCTOR MODULE, METHOD FOR MANUFACTURING SEMICONDUCTOR MODULE, SEMICONDUCTOR DEVICE, AND VEHICLE Aug 27, 2023 Pending
Array ( [id] => 19758143 [patent_doc_number] => 20250046708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => SEMICONDUCTOR DEVICE WITH PROTECTION LAYER AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/230183 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11749 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230183 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/230183
SEMICONDUCTOR DEVICE WITH PROTECTION LAYER AND METHOD FOR FABRICATING THE SAME Aug 3, 2023 Pending
Array ( [id] => 19758151 [patent_doc_number] => 20250046716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => MODIFIED REVERSE SELECTIVE BARRIER STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/365791 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8369 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -36 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365791 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/365791
MODIFIED REVERSE SELECTIVE BARRIER STRUCTURE Aug 3, 2023 Pending
Array ( [id] => 19842731 [patent_doc_number] => 12255131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Capacitor between two passivation layers with different etching rates [patent_app_type] => utility [patent_app_number] => 18/365009 [patent_app_country] => US [patent_app_date] => 2023-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6264 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18365009 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/365009
Capacitor between two passivation layers with different etching rates Aug 2, 2023 Issued
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