![](/images/general/no_picture/200_user.png)
John E Chapman Jr
Examiner (ID: 1729, Phone: (571)272-2191 , Office: P/2855 )
Most Active Art Unit | 2856 |
Art Unit(s) | 2861, 2855, 2761, 2212, 2856, 2605, 2899 |
Total Applications | 2356 |
Issued Applications | 1950 |
Pending Applications | 51 |
Abandoned Applications | 355 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4973011
[patent_doc_number] => 20070113014
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-17
[patent_title] => 'Weak referenced based eviction of persistent data from cache'
[patent_app_type] => utility
[patent_app_number] => 10/837222
[patent_app_country] => US
[patent_app_date] => 2004-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4016
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0113/20070113014.pdf
[firstpage_image] =>[orig_patent_app_number] => 10837222
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/837222 | Weak referenced based eviction of persistent data from cache | Apr 29, 2004 | Abandoned |
Array
(
[id] => 7471563
[patent_doc_number] => 20040199607
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-07
[patent_title] => 'Reconfiguration of storage system including multiple mass storage devices'
[patent_app_type] => new
[patent_app_number] => 10/826757
[patent_app_country] => US
[patent_app_date] => 2004-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 4314
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[patent_words_short_claim] => 86
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0199/20040199607.pdf
[firstpage_image] =>[orig_patent_app_number] => 10826757
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/826757 | Reconfiguration of storage system including multiple mass storage devices | Apr 14, 2004 | Issued |
Array
(
[id] => 7063170
[patent_doc_number] => 20050005075
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-06
[patent_title] => 'Multi-node computer system employing multiple memory response states'
[patent_app_type] => utility
[patent_app_number] => 10/821370
[patent_app_country] => US
[patent_app_date] => 2004-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 44
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[patent_no_of_words] => 47614
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[pdf_file] => publications/A1/0005/20050005075.pdf
[firstpage_image] =>[orig_patent_app_number] => 10821370
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/821370 | Multi-node computer system employing multiple memory response states | Apr 8, 2004 | Abandoned |
Array
(
[id] => 7091547
[patent_doc_number] => 20050010615
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-01-13
[patent_title] => 'Multi-node computer system implementing memory-correctable speculative proxy transactions'
[patent_app_type] => utility
[patent_app_number] => 10/821350
[patent_app_country] => US
[patent_app_date] => 2004-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 44
[patent_figures_cnt] => 44
[patent_no_of_words] => 47657
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 5
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0010/20050010615.pdf
[firstpage_image] =>[orig_patent_app_number] => 10821350
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/821350 | Multi-node computer system implementing memory-correctable speculative proxy transactions | Apr 8, 2004 | Abandoned |
Array
(
[id] => 7261959
[patent_doc_number] => 20040260885
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-23
[patent_title] => 'Multi-node computer system in which interfaces provide data to satisfy coherency transactions when no owning device present in modified global access state node'
[patent_app_type] => new
[patent_app_number] => 10/821393
[patent_app_country] => US
[patent_app_date] => 2004-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 44
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[patent_no_of_words] => 48010
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0260/20040260885.pdf
[firstpage_image] =>[orig_patent_app_number] => 10821393
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/821393 | Multi-node computer system in which interfaces provide data to satisfy coherency transactions when no owning device present in modified global access state node | Apr 8, 2004 | Issued |
Array
(
[id] => 6953844
[patent_doc_number] => 20050228939
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-13
[patent_title] => 'System and method for optimizing interconnections of components in a multichip memory module'
[patent_app_type] => utility
[patent_app_number] => 10/822275
[patent_app_country] => US
[patent_app_date] => 2004-04-08
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[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 5551
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[pdf_file] => publications/A1/0228/20050228939.pdf
[firstpage_image] =>[orig_patent_app_number] => 10822275
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/822275 | System and method for optimizing interconnections of components in a multichip memory module | Apr 7, 2004 | Issued |
Array
(
[id] => 7112862
[patent_doc_number] => 20050210318
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-22
[patent_title] => 'System and method for drive recovery following a drive failure'
[patent_app_type] => utility
[patent_app_number] => 10/805811
[patent_app_country] => US
[patent_app_date] => 2004-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3829
[patent_no_of_claims] => 20
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[pdf_file] => publications/A1/0210/20050210318.pdf
[firstpage_image] =>[orig_patent_app_number] => 10805811
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/805811 | System and method for drive recovery following a drive failure | Mar 21, 2004 | Abandoned |
Array
(
[id] => 7262449
[patent_doc_number] => 20050144512
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-30
[patent_title] => 'Redundant array of independent disks and conversion method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/801630
[patent_app_country] => US
[patent_app_date] => 2004-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3800
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 5
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0144/20050144512.pdf
[firstpage_image] =>[orig_patent_app_number] => 10801630
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/801630 | Redundant array of independent disks and conversion method thereof | Mar 14, 2004 | Abandoned |
Array
(
[id] => 7166814
[patent_doc_number] => 20050086447
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-21
[patent_title] => 'Program and apparatus for blocking information leaks, and storage medium for the program'
[patent_app_type] => utility
[patent_app_number] => 10/793271
[patent_app_country] => US
[patent_app_date] => 2004-03-05
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[patent_drawing_sheets_cnt] => 12
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[patent_no_of_words] => 7651
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[pdf_file] => publications/A1/0086/20050086447.pdf
[firstpage_image] =>[orig_patent_app_number] => 10793271
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/793271 | Program and apparatus for blocking information leaks, and storage medium for the program | Mar 4, 2004 | Abandoned |
Array
(
[id] => 7672150
[patent_doc_number] => 20040181629
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-16
[patent_title] => 'Information processing apparatus, information processing method and program'
[patent_app_type] => new
[patent_app_number] => 10/785063
[patent_app_country] => US
[patent_app_date] => 2004-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[pdf_file] => publications/A1/0181/20040181629.pdf
[firstpage_image] =>[orig_patent_app_number] => 10785063
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/785063 | Information processing apparatus, information processing method and program | Feb 24, 2004 | Issued |
Array
(
[id] => 7052439
[patent_doc_number] => 20050188158
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-25
[patent_title] => 'Cache memory with improved replacement policy'
[patent_app_type] => utility
[patent_app_number] => 10/786250
[patent_app_country] => US
[patent_app_date] => 2004-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 6069
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[pdf_file] => publications/A1/0188/20050188158.pdf
[firstpage_image] =>[orig_patent_app_number] => 10786250
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/786250 | Cache memory with improved replacement policy | Feb 24, 2004 | Abandoned |
Array
(
[id] => 7358628
[patent_doc_number] => 20040250038
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-09
[patent_title] => 'Information processing apparatus and memory access arranging method'
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[pdf_file] => publications/A1/0250/20040250038.pdf
[firstpage_image] =>[orig_patent_app_number] => 10764484
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/764484 | Information processing apparatus and memory access arranging method | Jan 26, 2004 | Issued |
Array
(
[id] => 116439
[patent_doc_number] => 07721062
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-05-18
[patent_title] => 'Method for detecting leaked buffer writes across file system consistency points'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/705470 | Method for detecting leaked buffer writes across file system consistency points | Nov 9, 2003 | Issued |
Array
(
[id] => 7259973
[patent_doc_number] => 20050076179
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[patent_issue_date] => 2005-04-07
[patent_title] => 'Cache optimized logical partitioning a symmetric multi-processor data processing system'
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[patent_app_number] => 10/677661
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[firstpage_image] =>[orig_patent_app_number] => 10677661
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/677661 | Cache optimized logical partitioning a symmetric multi-processor data processing system | Oct 1, 2003 | Abandoned |
Array
(
[id] => 313049
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[patent_kind] => B2
[patent_issue_date] => 2009-05-05
[patent_title] => 'Cache control method for node apparatus'
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[firstpage_image] =>[orig_patent_app_number] => 10663700
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/663700 | Cache control method for node apparatus | Sep 16, 2003 | Issued |
Array
(
[id] => 7085075
[patent_doc_number] => 20050050455
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-03
[patent_title] => 'Method and apparatus for supporting object caching in a web presentation architecture'
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[patent_app_date] => 2003-08-29
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[pdf_file] => publications/A1/0050/20050050455.pdf
[firstpage_image] =>[orig_patent_app_number] => 10652388
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/652388 | Method and apparatus for supporting object caching in a web presentation architecture | Aug 28, 2003 | Abandoned |
Array
(
[id] => 6968221
[patent_doc_number] => 20050235118
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-20
[patent_title] => 'Data storage circuit, data write method in the data storage circuit, and data storage device'
[patent_app_type] => utility
[patent_app_number] => 10/505431
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[firstpage_image] =>[orig_patent_app_number] => 10505431
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/505431 | Power saving data storage circuit, data writing method in the same, and data storage device | Mar 16, 2003 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/484322 | Non-volatile memory and non-volatile memory data rewriting method | Jul 18, 2002 | Issued |