Search

John E. Uselding

Examiner (ID: 6863, Phone: (571)270-5463 , Office: P/1763 )

Most Active Art Unit
1763
Art Unit(s)
4171, 1796, 1763
Total Applications
1454
Issued Applications
729
Pending Applications
129
Abandoned Applications
616

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6419972 [patent_doc_number] => 20100277231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => ' FILTERING ON CURRENT MODE DAISY CHAIN INPUTS' [patent_app_type] => utility [patent_app_number] => 12/719481 [patent_app_country] => US [patent_app_date] => 2010-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4644 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20100277231.pdf [firstpage_image] =>[orig_patent_app_number] => 12719481 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/719481
FILTERING ON CURRENT MODE DAISY CHAIN INPUTS Mar 7, 2010 Abandoned
Array ( [id] => 6619157 [patent_doc_number] => 20100225368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'PHASE-LOCKED LOOP CIRCUIT AND AN ASSOCIATED METHOD' [patent_app_type] => utility [patent_app_number] => 12/718291 [patent_app_country] => US [patent_app_date] => 2010-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4632 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20100225368.pdf [firstpage_image] =>[orig_patent_app_number] => 12718291 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/718291
Phase-locked loop circuit and an associated method Mar 4, 2010 Issued
Array ( [id] => 9627397 [patent_doc_number] => 08797083 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-05 [patent_title] => 'Methods of operating timers to inhibit timing error accumulation' [patent_app_type] => utility [patent_app_number] => 12/716492 [patent_app_country] => US [patent_app_date] => 2010-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5822 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12716492 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/716492
Methods of operating timers to inhibit timing error accumulation Mar 2, 2010 Issued
Array ( [id] => 6287306 [patent_doc_number] => 20100237914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'CLOCK DISTRIBUTION DEVICE AND CLOCK DISTRIBUTION METHOD' [patent_app_type] => utility [patent_app_number] => 12/716345 [patent_app_country] => US [patent_app_date] => 2010-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8595 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20100237914.pdf [firstpage_image] =>[orig_patent_app_number] => 12716345 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/716345
CLOCK DISTRIBUTION DEVICE AND CLOCK DISTRIBUTION METHOD Mar 2, 2010 Abandoned
Array ( [id] => 9228086 [patent_doc_number] => 08633757 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-01-21 [patent_title] => 'Low-noise, temperature-insensitive, voltage or current input, analog front end architecture' [patent_app_type] => utility [patent_app_number] => 12/713973 [patent_app_country] => US [patent_app_date] => 2010-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 5676 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12713973 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/713973
Low-noise, temperature-insensitive, voltage or current input, analog front end architecture Feb 25, 2010 Issued
Array ( [id] => 8436193 [patent_doc_number] => 08283968 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-09 [patent_title] => 'Analog switch' [patent_app_type] => utility [patent_app_number] => 12/712027 [patent_app_country] => US [patent_app_date] => 2010-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4311 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12712027 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/712027
Analog switch Feb 23, 2010 Issued
Array ( [id] => 11432645 [patent_doc_number] => 09570974 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'High-frequency switching circuit' [patent_app_type] => utility [patent_app_number] => 12/704737 [patent_app_country] => US [patent_app_date] => 2010-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9460 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12704737 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/704737
High-frequency switching circuit Feb 11, 2010 Issued
Array ( [id] => 6036943 [patent_doc_number] => 20110089992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'Systems for Accurate Multiplexing' [patent_app_type] => utility [patent_app_number] => 12/700895 [patent_app_country] => US [patent_app_date] => 2010-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3670 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20110089992.pdf [firstpage_image] =>[orig_patent_app_number] => 12700895 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/700895
Systems for accurate multiplexing Feb 4, 2010 Issued
Array ( [id] => 8956812 [patent_doc_number] => 08502594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-06 [patent_title] => 'Bootstrap transistor circuit' [patent_app_type] => utility [patent_app_number] => 12/628945 [patent_app_country] => US [patent_app_date] => 2009-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5757 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12628945 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/628945
Bootstrap transistor circuit Nov 30, 2009 Issued
Array ( [id] => 6193650 [patent_doc_number] => 20110025404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-03 [patent_title] => 'SWITCHES WITH VARIABLE CONTROL VOLTAGES' [patent_app_type] => utility [patent_app_number] => 12/623232 [patent_app_country] => US [patent_app_date] => 2009-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7990 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20110025404.pdf [firstpage_image] =>[orig_patent_app_number] => 12623232 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/623232
SWITCHES WITH VARIABLE CONTROL VOLTAGES Nov 19, 2009 Abandoned
Array ( [id] => 6414397 [patent_doc_number] => 20100141307 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'Frequency multiplier and method for frequency multiplying' [patent_app_type] => utility [patent_app_number] => 12/591375 [patent_app_country] => US [patent_app_date] => 2009-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3485 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20100141307.pdf [firstpage_image] =>[orig_patent_app_number] => 12591375 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/591375
Frequency multiplier and method for frequency multiplying Nov 17, 2009 Abandoned
Array ( [id] => 6146284 [patent_doc_number] => 20110018619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'INTEGRATED NEGATIVE VOLTAGE GENERATOR' [patent_app_type] => utility [patent_app_number] => 12/618544 [patent_app_country] => US [patent_app_date] => 2009-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5183 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20110018619.pdf [firstpage_image] =>[orig_patent_app_number] => 12618544 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/618544
INTEGRATED NEGATIVE VOLTAGE GENERATOR Nov 12, 2009 Abandoned
Array ( [id] => 5933474 [patent_doc_number] => 20110210781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'LEVEL SHIFTER' [patent_app_type] => utility [patent_app_number] => 13/063285 [patent_app_country] => US [patent_app_date] => 2009-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2867 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20110210781.pdf [firstpage_image] =>[orig_patent_app_number] => 13063285 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/063285
LEVEL SHIFTER Sep 8, 2009 Abandoned
Array ( [id] => 9390168 [patent_doc_number] => 08686778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-01 [patent_title] => 'Integrated pulse-control and enable latch circuit' [patent_app_type] => utility [patent_app_number] => 12/546529 [patent_app_country] => US [patent_app_date] => 2009-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6335 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12546529 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/546529
Integrated pulse-control and enable latch circuit Aug 23, 2009 Issued
Array ( [id] => 6551999 [patent_doc_number] => 20100045350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'Semiconductor Device and Amplification Device Generating Triangular Wave Synchronized with Clock Signal' [patent_app_type] => utility [patent_app_number] => 12/544336 [patent_app_country] => US [patent_app_date] => 2009-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3168 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20100045350.pdf [firstpage_image] =>[orig_patent_app_number] => 12544336 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/544336
Semiconductor Device and Amplification Device Generating Triangular Wave Synchronized with Clock Signal Aug 19, 2009 Abandoned
Array ( [id] => 6217080 [patent_doc_number] => 20100052743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT AND CIRCUIT OPERATION METHOD' [patent_app_type] => utility [patent_app_number] => 12/541358 [patent_app_country] => US [patent_app_date] => 2009-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 19711 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20100052743.pdf [firstpage_image] =>[orig_patent_app_number] => 12541358 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/541358
Semiconductor integrated circuit and circuit operation method Aug 13, 2009 Issued
Array ( [id] => 6146246 [patent_doc_number] => 20110018595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'METASTABILITY HARDENED SYNCHRONIZER CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/508577 [patent_app_country] => US [patent_app_date] => 2009-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5248 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20110018595.pdf [firstpage_image] =>[orig_patent_app_number] => 12508577 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/508577
METASTABILITY HARDENED SYNCHRONIZER CIRCUIT Jul 23, 2009 Abandoned
Array ( [id] => 6605877 [patent_doc_number] => 20100033223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-11 [patent_title] => 'FLIP-FLOP CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/507824 [patent_app_country] => US [patent_app_date] => 2009-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5254 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20100033223.pdf [firstpage_image] =>[orig_patent_app_number] => 12507824 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/507824
FLIP-FLOP CIRCUIT Jul 22, 2009 Abandoned
Array ( [id] => 14399229 [patent_doc_number] => 10312910 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Integrated circuit connection device [patent_app_type] => utility [patent_app_number] => 13/055580 [patent_app_country] => US [patent_app_date] => 2009-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2570 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13055580 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/055580
Integrated circuit connection device Jul 22, 2009 Issued
Array ( [id] => 12013264 [patent_doc_number] => 09806593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-31 [patent_title] => 'Drive circuit of power semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/059429 [patent_app_country] => US [patent_app_date] => 2009-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 8835 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 348 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13059429 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/059429
Drive circuit of power semiconductor device Jul 21, 2009 Issued
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