Search

John E. Uselding

Examiner (ID: 6863, Phone: (571)270-5463 , Office: P/1763 )

Most Active Art Unit
1763
Art Unit(s)
4171, 1796, 1763
Total Applications
1454
Issued Applications
729
Pending Applications
129
Abandoned Applications
616

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4864364 [patent_doc_number] => 20080143423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 11/943095 [patent_app_country] => US [patent_app_date] => 2007-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 20518 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0143/20080143423.pdf [firstpage_image] =>[orig_patent_app_number] => 11943095 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/943095
SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREFOR Nov 19, 2007 Abandoned
Array ( [id] => 4897340 [patent_doc_number] => 20080116953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-22 [patent_title] => 'FLIP-FLOP CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/943059 [patent_app_country] => US [patent_app_date] => 2007-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7239 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20080116953.pdf [firstpage_image] =>[orig_patent_app_number] => 11943059 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/943059
FLIP-FLOP CIRCUIT Nov 19, 2007 Abandoned
Array ( [id] => 8808531 [patent_doc_number] => 08446187 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-05-21 [patent_title] => 'Apparatus and method for power-on reset circuit with current comparison' [patent_app_type] => utility [patent_app_number] => 11/941858 [patent_app_country] => US [patent_app_date] => 2007-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2258 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 502 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11941858 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/941858
Apparatus and method for power-on reset circuit with current comparison Nov 15, 2007 Issued
Array ( [id] => 4902192 [patent_doc_number] => 20080111605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-15 [patent_title] => 'RESET CIRCUIT OF HIGH VOLTAGE CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/939431 [patent_app_country] => US [patent_app_date] => 2007-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3029 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20080111605.pdf [firstpage_image] =>[orig_patent_app_number] => 11939431 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/939431
Reset circuit of high voltage circuit Nov 12, 2007 Issued
Array ( [id] => 4749771 [patent_doc_number] => 20080157842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'MTCMOS Flip-Flop Circuit' [patent_app_type] => utility [patent_app_number] => 11/929933 [patent_app_country] => US [patent_app_date] => 2007-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3209 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157842.pdf [firstpage_image] =>[orig_patent_app_number] => 11929933 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/929933
MTCMOS Flip-Flop Circuit Oct 29, 2007 Abandoned
Array ( [id] => 4891267 [patent_doc_number] => 20080100364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'Multiphase clock generation circuit' [patent_app_type] => utility [patent_app_number] => 11/976855 [patent_app_country] => US [patent_app_date] => 2007-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7743 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0100/20080100364.pdf [firstpage_image] =>[orig_patent_app_number] => 11976855 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/976855
Multiphase clock generation circuit Oct 28, 2007 Issued
Array ( [id] => 5328428 [patent_doc_number] => 20090108905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'Dynamic NP-swappable body bias circuit' [patent_app_type] => utility [patent_app_number] => 11/976445 [patent_app_country] => US [patent_app_date] => 2007-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1529 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20090108905.pdf [firstpage_image] =>[orig_patent_app_number] => 11976445 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/976445
Dynamic NP-swappable body bias circuit Oct 23, 2007 Abandoned
Array ( [id] => 93562 [patent_doc_number] => 07733145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'Nonvolatile latch circuit and nonvolatile flip-flop circuit' [patent_app_type] => utility [patent_app_number] => 11/848864 [patent_app_country] => US [patent_app_date] => 2007-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 22 [patent_no_of_words] => 7476 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 456 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/733/07733145.pdf [firstpage_image] =>[orig_patent_app_number] => 11848864 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/848864
Nonvolatile latch circuit and nonvolatile flip-flop circuit Aug 30, 2007 Issued
Array ( [id] => 5320476 [patent_doc_number] => 20090058466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'DIFFERENTIAL PAIR CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/848859 [patent_app_country] => US [patent_app_date] => 2007-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5821 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20090058466.pdf [firstpage_image] =>[orig_patent_app_number] => 11848859 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/848859
DIFFERENTIAL PAIR CIRCUIT Aug 30, 2007 Abandoned
Array ( [id] => 4478007 [patent_doc_number] => 07868670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'Phase-locked loop (PLL) circuit and method' [patent_app_type] => utility [patent_app_number] => 11/842004 [patent_app_country] => US [patent_app_date] => 2007-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1680 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/868/07868670.pdf [firstpage_image] =>[orig_patent_app_number] => 11842004 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/842004
Phase-locked loop (PLL) circuit and method Aug 19, 2007 Issued
Array ( [id] => 5444622 [patent_doc_number] => 20090045848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-19 [patent_title] => 'PHASE-FREQUENCY DETECTOR WITH HIGH JITTER TOLERANCE' [patent_app_type] => utility [patent_app_number] => 11/839018 [patent_app_country] => US [patent_app_date] => 2007-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2118 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20090045848.pdf [firstpage_image] =>[orig_patent_app_number] => 11839018 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/839018
PHASE-FREQUENCY DETECTOR WITH HIGH JITTER TOLERANCE Aug 14, 2007 Abandoned
Array ( [id] => 4749765 [patent_doc_number] => 20080157836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'DELAY FIXING LOOP CIRCUIT FOR REDUCING SKEW BETWEEN EXTERNAL AND INTERNAL CLOCKS OR BETWEEN EXTERNAL CLOCK AND DATA, AND A CLOCK LOCKING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/778816 [patent_app_country] => US [patent_app_date] => 2007-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5060 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157836.pdf [firstpage_image] =>[orig_patent_app_number] => 11778816 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/778816
DELAY FIXING LOOP CIRCUIT FOR REDUCING SKEW BETWEEN EXTERNAL AND INTERNAL CLOCKS OR BETWEEN EXTERNAL CLOCK AND DATA, AND A CLOCK LOCKING METHOD THEREOF Jul 16, 2007 Abandoned
Array ( [id] => 4769313 [patent_doc_number] => 20080054971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-06 [patent_title] => 'PULSE WIDTH MODULATION CONTROL CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/774242 [patent_app_country] => US [patent_app_date] => 2007-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2441 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20080054971.pdf [firstpage_image] =>[orig_patent_app_number] => 11774242 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/774242
PULSE WIDTH MODULATION CONTROL CIRCUIT Jul 5, 2007 Abandoned
Array ( [id] => 4731762 [patent_doc_number] => 20080048740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'METHOD AND APPARATUS FOR GENERATING CLOCK SIGNAL' [patent_app_type] => utility [patent_app_number] => 11/773940 [patent_app_country] => US [patent_app_date] => 2007-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1879 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20080048740.pdf [firstpage_image] =>[orig_patent_app_number] => 11773940 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/773940
METHOD AND APPARATUS FOR GENERATING CLOCK SIGNAL Jul 4, 2007 Abandoned
Array ( [id] => 5346695 [patent_doc_number] => 20090002056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-01 [patent_title] => 'ACTIVE RESISTANCE CIRCUIT WITH CONTROLLABLE TEMPERATURE COEFFICIENT' [patent_app_type] => utility [patent_app_number] => 11/772190 [patent_app_country] => US [patent_app_date] => 2007-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2000 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20090002056.pdf [firstpage_image] =>[orig_patent_app_number] => 11772190 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/772190
ACTIVE RESISTANCE CIRCUIT WITH CONTROLLABLE TEMPERATURE COEFFICIENT Jun 29, 2007 Abandoned
Array ( [id] => 1077517 [patent_doc_number] => 07616034 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-11-10 [patent_title] => 'Circuit for controlling data output' [patent_app_type] => utility [patent_app_number] => 11/770880 [patent_app_country] => US [patent_app_date] => 2007-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 5067 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/616/07616034.pdf [firstpage_image] =>[orig_patent_app_number] => 11770880 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/770880
Circuit for controlling data output Jun 28, 2007 Issued
Array ( [id] => 4757159 [patent_doc_number] => 20080309384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'Initialization Circuitry Having Fuse Leakage Current Tolerance' [patent_app_type] => utility [patent_app_number] => 11/762317 [patent_app_country] => US [patent_app_date] => 2007-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5215 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0309/20080309384.pdf [firstpage_image] =>[orig_patent_app_number] => 11762317 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/762317
Initialization Circuitry Having Fuse Leakage Current Tolerance Jun 12, 2007 Abandoned
Array ( [id] => 4708703 [patent_doc_number] => 20080297229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'LOW POWER CMOS VOLTAGE REFERENCE CIRCUITS' [patent_app_type] => utility [patent_app_number] => 11/756023 [patent_app_country] => US [patent_app_date] => 2007-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3080 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0297/20080297229.pdf [firstpage_image] =>[orig_patent_app_number] => 11756023 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/756023
LOW POWER CMOS VOLTAGE REFERENCE CIRCUITS May 30, 2007 Abandoned
Array ( [id] => 4715991 [patent_doc_number] => 20080238513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Hysteresis Circuit Without Static Quiescent Current' [patent_app_type] => utility [patent_app_number] => 11/693657 [patent_app_country] => US [patent_app_date] => 2007-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3415 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20080238513.pdf [firstpage_image] =>[orig_patent_app_number] => 11693657 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/693657
Hysteresis Circuit Without Static Quiescent Current Mar 28, 2007 Abandoned
Array ( [id] => 304137 [patent_doc_number] => 07535278 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-05-19 [patent_title] => 'Circuits and methods of using parallel counter controlled delay lines to generate a clock signal' [patent_app_type] => utility [patent_app_number] => 11/717810 [patent_app_country] => US [patent_app_date] => 2007-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4514 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/535/07535278.pdf [firstpage_image] =>[orig_patent_app_number] => 11717810 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/717810
Circuits and methods of using parallel counter controlled delay lines to generate a clock signal Mar 12, 2007 Issued
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