
John E. Uselding
Examiner (ID: 6863, Phone: (571)270-5463 , Office: P/1763 )
| Most Active Art Unit | 1763 |
| Art Unit(s) | 4171, 1796, 1763 |
| Total Applications | 1454 |
| Issued Applications | 729 |
| Pending Applications | 129 |
| Abandoned Applications | 616 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
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[patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREFOR'
[patent_app_type] => utility
[patent_app_number] => 11/943095
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/943095 | SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREFOR | Nov 19, 2007 | Abandoned |
Array
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[patent_title] => 'FLIP-FLOP CIRCUIT'
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Array
(
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[patent_kind] => B1
[patent_issue_date] => 2013-05-21
[patent_title] => 'Apparatus and method for power-on reset circuit with current comparison'
[patent_app_type] => utility
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Array
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[patent_title] => 'RESET CIRCUIT OF HIGH VOLTAGE CIRCUIT'
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Array
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Array
(
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Array
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Array
(
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[patent_issue_date] => 2010-06-08
[patent_title] => 'Nonvolatile latch circuit and nonvolatile flip-flop circuit'
[patent_app_type] => utility
[patent_app_number] => 11/848864
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Array
(
[id] => 5320476
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[patent_title] => 'DIFFERENTIAL PAIR CIRCUIT'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/848859 | DIFFERENTIAL PAIR CIRCUIT | Aug 30, 2007 | Abandoned |
Array
(
[id] => 4478007
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[patent_title] => 'Phase-locked loop (PLL) circuit and method'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/842004 | Phase-locked loop (PLL) circuit and method | Aug 19, 2007 | Issued |
Array
(
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[patent_title] => 'PHASE-FREQUENCY DETECTOR WITH HIGH JITTER TOLERANCE'
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Array
(
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Array
(
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[patent_title] => 'PULSE WIDTH MODULATION CONTROL CIRCUIT'
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Array
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Array
(
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Array
(
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/756023 | LOW POWER CMOS VOLTAGE REFERENCE CIRCUITS | May 30, 2007 | Abandoned |
Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/717810 | Circuits and methods of using parallel counter controlled delay lines to generate a clock signal | Mar 12, 2007 | Issued |