
John G. Mills
Examiner (ID: 17861)
| Most Active Art Unit | 2307 |
| Art Unit(s) | 2771, 2171, 2307 |
| Total Applications | 484 |
| Issued Applications | 430 |
| Pending Applications | 1 |
| Abandoned Applications | 53 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4026133
[patent_doc_number] => 05890149
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-30
[patent_title] => 'Organization training, coaching and indexing system'
[patent_app_type] => 1
[patent_app_number] => 8/667803
[patent_app_country] => US
[patent_app_date] => 1996-06-20
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[pdf_file] => patents/05/890/05890149.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/667803 | Organization training, coaching and indexing system | Jun 19, 1996 | Issued |
Array
(
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[patent_kind] => NA
[patent_issue_date] => 1990-10-16
[patent_title] => 'Harvard architecture microprocessor with arithmetic operations and control tasks for data transfer handled simultaneously'
[patent_app_type] => 1
[patent_app_number] => 7/453027
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[patent_app_date] => 1989-12-22
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Array
(
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[patent_issue_date] => 1990-09-11
[patent_title] => 'Sequentially processing data in a cached data storage system'
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[patent_app_date] => 1989-09-14
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Array
(
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[patent_kind] => NA
[patent_issue_date] => 1991-08-13
[patent_title] => 'Data shifting and rotating apparatus'
[patent_app_type] => 2
[patent_app_number] => 7/397342
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[patent_app_date] => 1989-08-22
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Array
(
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[patent_issue_date] => 1991-03-05
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/390784 | Circuit to arbitrate multiple requests for memory access | Aug 7, 1989 | Issued |
Array
(
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[patent_issue_date] => 1989-12-26
[patent_title] => 'Clock disabling circuit'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/384875 | Clock disabling circuit | Jul 20, 1989 | Issued |
Array
(
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[pdf_file] => patents/04/945/04945511.pdf
[firstpage_image] =>[orig_patent_app_number] => 371961
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/371961 | Improved pipelined processor with two stage decoder for exchanging register values for similar operand instructions | Jun 26, 1989 | Issued |
Array
(
[id] => 2655526
[patent_doc_number] => 04980857
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[patent_kind] => NA
[patent_issue_date] => 1990-12-25
[patent_title] => 'Operations controller for a fault tolerant multiple node processing system'
[patent_app_type] => 1
[patent_app_number] => 7/362957
[patent_app_country] => US
[patent_app_date] => 1989-06-07
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[patent_drawing_sheets_cnt] => 58
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[pdf_file] => patents/04/980/04980857.pdf
[firstpage_image] =>[orig_patent_app_number] => 362957
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/362957 | Operations controller for a fault tolerant multiple node processing system | Jun 6, 1989 | Issued |
| 07/324281 | ASYNCHRONOUS ARBITER CIRCUIT | Mar 14, 1989 | Abandoned |
Array
(
[id] => 2617968
[patent_doc_number] => 04903200
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[patent_issue_date] => 1990-02-20
[patent_title] => 'Point of sale apparatus'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/323072 | Point of sale apparatus | Mar 9, 1989 | Issued |
Array
(
[id] => 2563781
[patent_doc_number] => 04897810
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[patent_issue_date] => 1990-01-30
[patent_title] => 'Asynchronous interrupt status bit circuit'
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[patent_app_number] => 7/318098
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[pdf_file] => patents/04/897/04897810.pdf
[firstpage_image] =>[orig_patent_app_number] => 318098
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/318098 | Asynchronous interrupt status bit circuit | Mar 1, 1989 | Issued |
Array
(
[id] => 2626642
[patent_doc_number] => 04969120
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[patent_issue_date] => 1990-11-06
[patent_title] => 'Data processing system for time shared access to a time slotted bus'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/310406 | Data processing system for time shared access to a time slotted bus | Feb 12, 1989 | Issued |
Array
(
[id] => 2602787
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[patent_issue_date] => 1990-06-12
[patent_title] => 'Apparatus for maintaining consistency of a cache memory with a primary memory'
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Array
(
[id] => 2654856
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[patent_title] => 'Event driven executive'
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[firstpage_image] =>[orig_patent_app_number] => 298291
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/298291 | Event driven executive | Jan 16, 1989 | Issued |
| 07/295610 | PROGRAMMABLE RECEIVER FIFO TRIGGER LEVEL IN AN ASYNCHRONOUS COMMUNICATIONS ELEMENT | Jan 9, 1989 | Abandoned |
Array
(
[id] => 2527646
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[patent_title] => 'Programmable controller (\"PC\") with co-processing architecture'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/292623 | Programmable controller ("PC") with co-processing architecture | Dec 28, 1988 | Issued |
Array
(
[id] => 2633312
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[patent_title] => 'Method for canonical ordering of binary data for portable operating systems'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/277835 | Diskette drive/storage unit assembly | Nov 29, 1988 | Issued |
Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/273035 | Automatic programming method for outputting figure elements of parts as well as part profile descriptions in response to a part profile request | Nov 6, 1988 | Issued |