John G. Mills

Array ( [id] => 2390231 [patent_doc_number] => 04775955 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-10-04 [patent_title] => 'Cache coherence mechanism based on locking' [patent_app_type] => 1 [patent_app_number] => 7/134676 [patent_app_country] => US [patent_app_date] => 1987-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6393 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 361 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/775/04775955.pdf [firstpage_image] =>[orig_patent_app_number] => 134676 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2677718 [patent_doc_number] => 04954956 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-09-04 [patent_title] => 'Data processing apparatus having function of providing helpful information after excessive time lapse from last input operation' [patent_app_type] => 1 [patent_app_number] => 7/131405 [patent_app_country] => US [patent_app_date] => 1987-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 7545 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/954/04954956.pdf [firstpage_image] =>[orig_patent_app_number] => 131405 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2481847 [patent_doc_number] => 04887235 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-12-12 [patent_title] => 'Symbolic language data processing system' [patent_app_type] => 1 [patent_app_number] => 7/129921 [patent_app_country] => US [patent_app_date] => 1987-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 26375 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/887/04887235.pdf [firstpage_image] =>[orig_patent_app_number] => 129921 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2640956 [patent_doc_number] => 04937736 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-06-26 [patent_title] => 'Memory controller for protected memory with automatic access granting capability' [patent_app_type] => 1 [patent_app_number] => 7/126529 [patent_app_country] => US [patent_app_date] => 1987-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2778 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/937/04937736.pdf [firstpage_image] =>[orig_patent_app_number] => 126529 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2451196 [patent_doc_number] => 04792919 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-12-20 [patent_title] => 'Word processor' [patent_app_type] => 1 [patent_app_number] => 7/124368 [patent_app_country] => US [patent_app_date] => 1987-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 37 [patent_no_of_words] => 8622 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/792/04792919.pdf [firstpage_image] =>[orig_patent_app_number] => 124368 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2715798 [patent_doc_number] => 04992972 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-12 [patent_title] => 'Flexible context searchable on-line information system with help files and modules for on-line computer system documentation' [patent_app_type] => 1 [patent_app_number] => 7/122154 [patent_app_country] => US [patent_app_date] => 1987-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5765 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 477 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/992/04992972.pdf [firstpage_image] =>[orig_patent_app_number] => 122154 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2572683 [patent_doc_number] => 04835735 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-05-30 [patent_title] => 'Card image data processing system' [patent_app_type] => 1 [patent_app_number] => 7/111117 [patent_app_country] => US [patent_app_date] => 1987-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 80 [patent_figures_cnt] => 92 [patent_no_of_words] => 14450 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/835/04835735.pdf [firstpage_image] =>[orig_patent_app_number] => 111117 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2499131 [patent_doc_number] => 04850726 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-07-25 [patent_title] => 'Word processor provided with an automatic tabset means' [patent_app_type] => 1 [patent_app_number] => 7/105807 [patent_app_country] => US [patent_app_date] => 1987-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 4137 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/850/04850726.pdf [firstpage_image] =>[orig_patent_app_number] => 105807 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2500677 [patent_doc_number] => 04860245 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-08-22 [patent_title] => 'Vector data processing system comprising an I/O control for each vector data processor and another I/O control for at least one other vector data processor' [patent_app_type] => 1 [patent_app_number] => 7/105028 [patent_app_country] => US [patent_app_date] => 1987-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5709 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/860/04860245.pdf [firstpage_image] =>[orig_patent_app_number] => 105028 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2772362 [patent_doc_number] => 04994961 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-19 [patent_title] => 'Coprocessor instruction format' [patent_app_type] => 1 [patent_app_number] => 7/098441 [patent_app_country] => US [patent_app_date] => 1987-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 13931 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/994/04994961.pdf [firstpage_image] =>[orig_patent_app_number] => 098441 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2759598 [patent_doc_number] => 05021991 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-04 [patent_title] => 'Coprocessor instruction format' [patent_app_type] => 1 [patent_app_number] => 7/098442 [patent_app_country] => US [patent_app_date] => 1987-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 13937 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/021/05021991.pdf [firstpage_image] =>[orig_patent_app_number] => 098442 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2453050 [patent_doc_number] => 04745574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-05-17 [patent_title] => 'Microcode testing of PLA\'s in a data processor' [patent_app_type] => 1 [patent_app_number] => 7/097276 [patent_app_country] => US [patent_app_date] => 1987-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3427 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/745/04745574.pdf [firstpage_image] =>[orig_patent_app_number] => 097276 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2422628 [patent_doc_number] => 04744049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-05-10 [patent_title] => 'Microcode testing of a cache in a data processor' [patent_app_type] => 1 [patent_app_number] => 7/097277 [patent_app_country] => US [patent_app_date] => 1987-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3440 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/744/04744049.pdf [firstpage_image] =>[orig_patent_app_number] => 097277 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2557880 [patent_doc_number] => 04811274 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-03-07 [patent_title] => 'Method and apparatus for selectively evaluating an effective address for a coprocessor' [patent_app_type] => 1 [patent_app_number] => 7/095718 [patent_app_country] => US [patent_app_date] => 1987-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 14080 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/811/04811274.pdf [firstpage_image] =>[orig_patent_app_number] => 095718 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2607438 [patent_doc_number] => 04922414 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-05-01 [patent_title] => 'Symbolic language data processing system' [patent_app_type] => 1 [patent_app_number] => 7/078724 [patent_app_country] => US [patent_app_date] => 1987-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 20430 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/922/04922414.pdf [firstpage_image] =>[orig_patent_app_number] => 078724 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2531012 [patent_doc_number] => 04885770 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-12-05 [patent_title] => 'Boot system for distributed digital data processing system' [patent_app_type] => 1 [patent_app_number] => 7/093811 [patent_app_country] => US [patent_app_date] => 1987-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3021 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/885/04885770.pdf [firstpage_image] =>[orig_patent_app_number] => 093811 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2426920 [patent_doc_number] => 04748586 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-05-31 [patent_title] => 'Data processing system with interrupt facilities' [patent_app_type] => 1 [patent_app_number] => 7/093139 [patent_app_country] => US [patent_app_date] => 1987-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7780 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/748/04748586.pdf [firstpage_image] =>[orig_patent_app_number] => 093139 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2641853 [patent_doc_number] => 04937783 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-06-26 [patent_title] => 'Peripheral controller for executing multiple event-count instructions and nonevent-count instructions in a prescribed parallel sequence' [patent_app_type] => 1 [patent_app_number] => 7/086323 [patent_app_country] => US [patent_app_date] => 1987-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4082 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/937/04937783.pdf [firstpage_image] =>[orig_patent_app_number] => 086323 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2635246 [patent_doc_number] => 04951193 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-08-21 [patent_title] => 'Parallel computer with distributed shared memories and distributed task activating circuits' [patent_app_type] => 1 [patent_app_number] => 7/085646 [patent_app_country] => US [patent_app_date] => 1987-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 13466 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/951/04951193.pdf [firstpage_image] =>[orig_patent_app_number] => 085646 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2677778 [patent_doc_number] => 04905190 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-02-27 [patent_title] => 'Multiprogram control information processing system with process roll-in from main memory' [patent_app_type] => 1 [patent_app_number] => 7/082558 [patent_app_country] => US [patent_app_date] => 1987-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2493 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 323 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/905/04905190.pdf [firstpage_image] =>[orig_patent_app_number] => 082558 [rel_patent_id] =>[rel_patent_doc_number] =>)