Search

John G. Pickett

Supervisory Patent Examiner (ID: 14915, Phone: (571)272-4560 , Office: P/3728 )

Most Active Art Unit
3728
Art Unit(s)
3788, 3736, 3782, 3741, 3728
Total Applications
932
Issued Applications
383
Pending Applications
22
Abandoned Applications
527

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12236164 [patent_doc_number] => 20180069027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'PREVENTING STRAINED FIN RELAXATION' [patent_app_type] => utility [patent_app_number] => 15/796429 [patent_app_country] => US [patent_app_date] => 2017-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6201 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15796429 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/796429
Preventing strained fin relaxation Oct 26, 2017 Issued
Array ( [id] => 13808503 [patent_doc_number] => 10181520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-15 [patent_title] => Method of fabricating electrically erasable programmable non-volatile memory cell structure [patent_app_type] => utility [patent_app_number] => 15/793979 [patent_app_country] => US [patent_app_date] => 2017-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 8183 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15793979 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/793979
Method of fabricating electrically erasable programmable non-volatile memory cell structure Oct 24, 2017 Issued
Array ( [id] => 12188766 [patent_doc_number] => 20180047702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'BUMPLESS BUILD-UP LAYER PACKAGE WITH A PRE-STACKED MICROELECTRONIC DEVICES' [patent_app_type] => utility [patent_app_number] => 15/791292 [patent_app_country] => US [patent_app_date] => 2017-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2843 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15791292 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/791292
BUMPLESS BUILD-UP LAYER PACKAGE WITH A PRE-STACKED MICROELECTRONIC DEVICES Oct 22, 2017 Abandoned
Array ( [id] => 16272554 [patent_doc_number] => 20200274042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => LIGHT EMITTING DEVICE PACKAGE AND LIGHT SOURCE APPARATUS [patent_app_type] => utility [patent_app_number] => 16/067484 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 33847 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16067484 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/067484
Light emitting device package and light source apparatus Sep 28, 2017 Issued
Array ( [id] => 14267891 [patent_doc_number] => 10283517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Semiconductor memory device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/703006 [patent_app_country] => US [patent_app_date] => 2017-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 10523 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15703006 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/703006
Semiconductor memory device and method of manufacturing the same Sep 12, 2017 Issued
Array ( [id] => 12122324 [patent_doc_number] => 20180005909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING SUCH DEVICES' [patent_app_type] => utility [patent_app_number] => 15/702225 [patent_app_country] => US [patent_app_date] => 2017-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8640 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15702225 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/702225
Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices Sep 11, 2017 Issued
Array ( [id] => 13320755 [patent_doc_number] => 20180211915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => CONNECTING BAR [patent_app_type] => utility [patent_app_number] => 15/700960 [patent_app_country] => US [patent_app_date] => 2017-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15700960 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/700960
Connecting bar Sep 10, 2017 Issued
Array ( [id] => 14049605 [patent_doc_number] => 20190080910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-14 [patent_title] => LATTICE MATCHED EPITAXIAL OXIDE LAYER FOR A SUPER STEEP RETROGRADE WELL [patent_app_type] => utility [patent_app_number] => 15/701312 [patent_app_country] => US [patent_app_date] => 2017-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5472 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15701312 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/701312
Lattice matched epitaxial oxide layer for a super steep retrograde well Sep 10, 2017 Issued
Array ( [id] => 14707075 [patent_doc_number] => 10381296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Semiconductor device package and a method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/699810 [patent_app_country] => US [patent_app_date] => 2017-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 42 [patent_no_of_words] => 9811 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15699810 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/699810
Semiconductor device package and a method of manufacturing the same Sep 7, 2017 Issued
Array ( [id] => 13819727 [patent_doc_number] => 10186641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-22 [patent_title] => Light emitting device [patent_app_type] => utility [patent_app_number] => 15/697452 [patent_app_country] => US [patent_app_date] => 2017-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 6368 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15697452 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/697452
Light emitting device Sep 6, 2017 Issued
Array ( [id] => 13228761 [patent_doc_number] => 10128162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => Method of manufacturing semiconductor device [patent_app_type] => utility [patent_app_number] => 15/696606 [patent_app_country] => US [patent_app_date] => 2017-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2741 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15696606 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/696606
Method of manufacturing semiconductor device Sep 5, 2017 Issued
Array ( [id] => 12243193 [patent_doc_number] => 20180076056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'ETCHING DEVICE, SUBSTRATE PROCESSING APPARATUS, ETCHING METHOD AND SUBSTRATE PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 15/696611 [patent_app_country] => US [patent_app_date] => 2017-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9516 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15696611 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/696611
Etching device, substrate processing apparatus, etching method and substrate processing method Sep 5, 2017 Issued
Array ( [id] => 13667681 [patent_doc_number] => 10164022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => FinFETs with strained well regions [patent_app_type] => utility [patent_app_number] => 15/688214 [patent_app_country] => US [patent_app_date] => 2017-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 27 [patent_no_of_words] => 6954 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15688214 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/688214
FinFETs with strained well regions Aug 27, 2017 Issued
Array ( [id] => 12095503 [patent_doc_number] => 20170352596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'FinFETs with Strained Well Regions' [patent_app_type] => utility [patent_app_number] => 15/687753 [patent_app_country] => US [patent_app_date] => 2017-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3488 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687753 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/687753
FinFETs with strained well regions Aug 27, 2017 Issued
Array ( [id] => 16394665 [patent_doc_number] => 20200335606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => VERTICAL TUNNELING FIELD-EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/303714 [patent_app_country] => US [patent_app_date] => 2017-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5369 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16303714 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/303714
VERTICAL TUNNELING FIELD-EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME Aug 21, 2017 Abandoned
Array ( [id] => 13419995 [patent_doc_number] => 20180261540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 15/679444 [patent_app_country] => US [patent_app_date] => 2017-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15679444 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/679444
Integrated circuit device Aug 16, 2017 Issued
Array ( [id] => 12236217 [patent_doc_number] => 20180069080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-08 [patent_title] => 'LOW-VOLTAGE CHARGE-COUPLED DEVICES WITH A HETEROSTRUCTURE CHARGE-STORAGE WELL' [patent_app_type] => utility [patent_app_number] => 15/679003 [patent_app_country] => US [patent_app_date] => 2017-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7257 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15679003 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/679003
Low-voltage charge-coupled devices with a heterostructure charge-storage well Aug 15, 2017 Issued
Array ( [id] => 12693064 [patent_doc_number] => 20180122854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/679084 [patent_app_country] => US [patent_app_date] => 2017-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13163 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15679084 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/679084
Electronic device and method for fabricating the same Aug 15, 2017 Issued
Array ( [id] => 12223600 [patent_doc_number] => 20180061961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'METHOD FOR MANUFACTURING A BIPOLAR JUNCTION TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 15/678152 [patent_app_country] => US [patent_app_date] => 2017-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4347 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15678152 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/678152
Method for manufacturing a bipolar junction transistor Aug 15, 2017 Issued
Array ( [id] => 12849304 [patent_doc_number] => 20180174941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND A CHIP STACK PACKAGE HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 15/678197 [patent_app_country] => US [patent_app_date] => 2017-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15678197 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/678197
Semiconductor memory device and a chip stack package having the same Aug 15, 2017 Issued
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