
John J. Figueroa
Examiner (ID: 15617, Phone: (571)272-8916 , Office: P/1768 )
| Most Active Art Unit | 1768 |
| Art Unit(s) | 1768, 1772, 1796, 1763, 1712, 1765 |
| Total Applications | 1556 |
| Issued Applications | 1186 |
| Pending Applications | 112 |
| Abandoned Applications | 275 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16803444
[patent_doc_number] => 10998400
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-05-04
[patent_title] => Semiconductor device, inverter circuit, driving device, vehicle, and elevator
[patent_app_type] => utility
[patent_app_number] => 16/555291
[patent_app_country] => US
[patent_app_date] => 2019-08-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 12942
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 434
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16555291
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/555291 | Semiconductor device, inverter circuit, driving device, vehicle, and elevator | Aug 28, 2019 | Issued |
Array
(
[id] => 16928457
[patent_doc_number] => 11049949
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-29
[patent_title] => Gate-all-around gradient-doped nano-sheet complementary inverter and method of making the same
[patent_app_type] => utility
[patent_app_number] => 16/554537
[patent_app_country] => US
[patent_app_date] => 2019-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 16
[patent_no_of_words] => 4921
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 296
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16554537
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/554537 | Gate-all-around gradient-doped nano-sheet complementary inverter and method of making the same | Aug 27, 2019 | Issued |
Array
(
[id] => 16536506
[patent_doc_number] => 10879119
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-29
[patent_title] => Method for fabricating a semiconductor device
[patent_app_type] => utility
[patent_app_number] => 16/552727
[patent_app_country] => US
[patent_app_date] => 2019-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 38
[patent_no_of_words] => 7110
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16552727
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/552727 | Method for fabricating a semiconductor device | Aug 26, 2019 | Issued |
Array
(
[id] => 15260505
[patent_doc_number] => 20190378986
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-12
[patent_title] => ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/549413
[patent_app_country] => US
[patent_app_date] => 2019-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9484
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 391
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16549413
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/549413 | Organic light-emitting display apparatus and method of manufacturing the same | Aug 22, 2019 | Issued |
Array
(
[id] => 16684296
[patent_doc_number] => 10943786
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-09
[patent_title] => Semiconductor device with self-aligned carbon nanotube gate
[patent_app_type] => utility
[patent_app_number] => 16/547948
[patent_app_country] => US
[patent_app_date] => 2019-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 3251
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16547948
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/547948 | Semiconductor device with self-aligned carbon nanotube gate | Aug 21, 2019 | Issued |
Array
(
[id] => 18073707
[patent_doc_number] => 11532547
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-20
[patent_title] => Interconnect structures with low-aspect-ratio contact vias
[patent_app_type] => utility
[patent_app_number] => 16/547732
[patent_app_country] => US
[patent_app_date] => 2019-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 6084
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16547732
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/547732 | Interconnect structures with low-aspect-ratio contact vias | Aug 21, 2019 | Issued |
Array
(
[id] => 16637917
[patent_doc_number] => 10916432
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-09
[patent_title] => Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device
[patent_app_type] => utility
[patent_app_number] => 16/541624
[patent_app_country] => US
[patent_app_date] => 2019-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 15
[patent_no_of_words] => 8425
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16541624
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/541624 | Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device | Aug 14, 2019 | Issued |
Array
(
[id] => 16668552
[patent_doc_number] => 10937810
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-02
[patent_title] => Sub-fin removal for SOI like isolation with uniform active fin height
[patent_app_type] => utility
[patent_app_number] => 16/541429
[patent_app_country] => US
[patent_app_date] => 2019-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 25
[patent_no_of_words] => 5332
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16541429
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/541429 | Sub-fin removal for SOI like isolation with uniform active fin height | Aug 14, 2019 | Issued |
Array
(
[id] => 15841307
[patent_doc_number] => 20200135936
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-04-30
[patent_title] => THIN FILM TRANSISTOR AND METHOD OF FABRICATING THE SAME, DISPLAY SUBSTRATE AND METHOD OF FABRICATING THE SAME, DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/536874
[patent_app_country] => US
[patent_app_date] => 2019-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4435
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16536874
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/536874 | Thin film transistor and method of fabricating the same, display substrate and method of fabricating the same, display device | Aug 8, 2019 | Issued |
Array
(
[id] => 16653371
[patent_doc_number] => 10930564
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-23
[patent_title] => Metal gate structure cutting process
[patent_app_type] => utility
[patent_app_number] => 16/536913
[patent_app_country] => US
[patent_app_date] => 2019-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 8335
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16536913
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/536913 | Metal gate structure cutting process | Aug 8, 2019 | Issued |
Array
(
[id] => 16707606
[patent_doc_number] => 10957550
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-23
[patent_title] => Semiconductor structure and formation method thereof
[patent_app_type] => utility
[patent_app_number] => 16/537072
[patent_app_country] => US
[patent_app_date] => 2019-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 10224
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16537072
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/537072 | Semiconductor structure and formation method thereof | Aug 8, 2019 | Issued |
Array
(
[id] => 15184899
[patent_doc_number] => 20190363041
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-28
[patent_title] => DEVICE WITH PILLAR-SHAPED COMPONENTS
[patent_app_type] => utility
[patent_app_number] => 16/535160
[patent_app_country] => US
[patent_app_date] => 2019-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8959
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16535160
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/535160 | Device with pillar-shaped components | Aug 7, 2019 | Issued |
Array
(
[id] => 15093007
[patent_doc_number] => 20190341315
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-07
[patent_title] => REPLACEMENT GATE FORMATION WITH ANGLED ETCH AND DEPOSITION
[patent_app_type] => utility
[patent_app_number] => 16/515576
[patent_app_country] => US
[patent_app_date] => 2019-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4864
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 63
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16515576
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/515576 | Replacement gate formation with angled etch and deposition | Jul 17, 2019 | Issued |
Array
(
[id] => 16566901
[patent_doc_number] => 10892278
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-01-12
[patent_title] => Three-dimensional semiconductor devices
[patent_app_type] => utility
[patent_app_number] => 16/509169
[patent_app_country] => US
[patent_app_date] => 2019-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 22
[patent_no_of_words] => 13069
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16509169
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/509169 | Three-dimensional semiconductor devices | Jul 10, 2019 | Issued |
Array
(
[id] => 14939069
[patent_doc_number] => 20190305173
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-10-03
[patent_title] => BURIED ACTIVATED p-(Al,In)GaN LAYERS
[patent_app_type] => utility
[patent_app_number] => 16/444596
[patent_app_country] => US
[patent_app_date] => 2019-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17547
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -29
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16444596
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/444596 | Buried activated p-(Al,In)GaN layers | Jun 17, 2019 | Issued |
Array
(
[id] => 14904529
[patent_doc_number] => 20190296030
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-26
[patent_title] => MEMORY CELL, NONVOLATILE SEMICONDUCTOR STORAGE DEVICE, AND METHOD FOR MANUFACTURING NONVOLATILE SEMICONDUCTOR STORAGE DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/434373
[patent_app_country] => US
[patent_app_date] => 2019-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 21879
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 251
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16434373
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/434373 | Memory cell, nonvolatile semiconductor storage device, and method for manufacturing nonvolatile semiconductor storage device | Jun 6, 2019 | Issued |
Array
(
[id] => 17366024
[patent_doc_number] => 11233055
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-01-25
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 16/431778
[patent_app_country] => US
[patent_app_date] => 2019-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 38
[patent_no_of_words] => 19715
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16431778
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/431778 | Semiconductor device | Jun 4, 2019 | Issued |
Array
(
[id] => 14875705
[patent_doc_number] => 20190288094
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-19
[patent_title] => Semiconductor Device with Separation Regions
[patent_app_type] => utility
[patent_app_number] => 16/430970
[patent_app_country] => US
[patent_app_date] => 2019-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8693
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16430970
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/430970 | Semiconductor device with separation regions | Jun 3, 2019 | Issued |
Array
(
[id] => 14904695
[patent_doc_number] => 20190296113
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-26
[patent_title] => METHOD OF MAKING A GALLIUM NITRIDE DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/424727
[patent_app_country] => US
[patent_app_date] => 2019-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11222
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16424727
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/424727 | Method of making a gallium nitride device | May 28, 2019 | Issued |
Array
(
[id] => 14785195
[patent_doc_number] => 20190267495
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-29
[patent_title] => Transistors Comprising At Least One of GaP, GaN, and GaAs
[patent_app_type] => utility
[patent_app_number] => 16/406385
[patent_app_country] => US
[patent_app_date] => 2019-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5687
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16406385
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/406385 | Transistors comprising at least one of GaP, GaN, and GaAs | May 7, 2019 | Issued |