Search

John J. Figueroa

Examiner (ID: 15617, Phone: (571)272-8916 , Office: P/1768 )

Most Active Art Unit
1768
Art Unit(s)
1768, 1772, 1796, 1763, 1712, 1765
Total Applications
1556
Issued Applications
1186
Pending Applications
112
Abandoned Applications
275

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16739079 [patent_doc_number] => 10964746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Deep trench isolation shrinkage method for enhanced device performance [patent_app_type] => utility [patent_app_number] => 16/405102 [patent_app_country] => US [patent_app_date] => 2019-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4720 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16405102 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/405102
Deep trench isolation shrinkage method for enhanced device performance May 6, 2019 Issued
Array ( [id] => 14753213 [patent_doc_number] => 20190259780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => INTEGRATED CIRCUITS (ICS) ON A GLASS SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/402713 [patent_app_country] => US [patent_app_date] => 2019-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16799 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16402713 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/402713
Integrated circuits (ICs) on a glass substrate May 2, 2019 Issued
Array ( [id] => 14753415 [patent_doc_number] => 20190259881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => VERTICAL MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/400443 [patent_app_country] => US [patent_app_date] => 2019-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16400443 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/400443
Vertical memory device Apr 30, 2019 Issued
Array ( [id] => 14753541 [patent_doc_number] => 20190259944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => Resistance Variable Memory Structure and Method of Forming the Same [patent_app_type] => utility [patent_app_number] => 16/398633 [patent_app_country] => US [patent_app_date] => 2019-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16398633 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/398633
Resistance variable memory structure and method of forming the same Apr 29, 2019 Issued
Array ( [id] => 16394523 [patent_doc_number] => 20200335464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => ELECTRICAL BINDING STRUCTURE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/390018 [patent_app_country] => US [patent_app_date] => 2019-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6663 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16390018 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/390018
Electrical binding structure and method of forming the same Apr 21, 2019 Issued
Array ( [id] => 16653508 [patent_doc_number] => 10930701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Light-emitting element having a plurality of light-emitting structures [patent_app_type] => utility [patent_app_number] => 16/390899 [patent_app_country] => US [patent_app_date] => 2019-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 4422 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16390899 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/390899
Light-emitting element having a plurality of light-emitting structures Apr 21, 2019 Issued
Array ( [id] => 16394498 [patent_doc_number] => 20200335439 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-22 [patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/389992 [patent_app_country] => US [patent_app_date] => 2019-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7761 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16389992 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/389992
Semiconductor package and manufacturing method thereof Apr 20, 2019 Issued
Array ( [id] => 15030425 [patent_doc_number] => 20190326217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => ELECTRONIC DEVICE WITH SHORT CIRCUIT PROTECTION ELEMENT, FABRICATION METHOD AND DESIGN METHOD [patent_app_type] => utility [patent_app_number] => 16/389866 [patent_app_country] => US [patent_app_date] => 2019-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3528 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16389866 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/389866
Electronic device with short circuit protection element, fabrication method and design method Apr 18, 2019 Issued
Array ( [id] => 16264730 [patent_doc_number] => 10756178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Self-limiting and confining epitaxial nucleation [patent_app_type] => utility [patent_app_number] => 16/388035 [patent_app_country] => US [patent_app_date] => 2019-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 6537 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16388035 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/388035
Self-limiting and confining epitaxial nucleation Apr 17, 2019 Issued
Array ( [id] => 16410034 [patent_doc_number] => 10818598 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Methods for reducing dual damascene distortion [patent_app_type] => utility [patent_app_number] => 16/388547 [patent_app_country] => US [patent_app_date] => 2019-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5057 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16388547 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/388547
Methods for reducing dual damascene distortion Apr 17, 2019 Issued
Array ( [id] => 16264729 [patent_doc_number] => 10756177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Self-limiting and confining epitaxial nucleation [patent_app_type] => utility [patent_app_number] => 16/388028 [patent_app_country] => US [patent_app_date] => 2019-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 6537 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16388028 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/388028
Self-limiting and confining epitaxial nucleation Apr 17, 2019 Issued
Array ( [id] => 15046125 [patent_doc_number] => 20190334067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/384948 [patent_app_country] => US [patent_app_date] => 2019-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7725 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16384948 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/384948
Electronic device Apr 15, 2019 Issued
Array ( [id] => 17032969 [patent_doc_number] => 11094789 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-17 [patent_title] => Thin film transistor and method for manufacturing the same, array substrate, and display device [patent_app_type] => utility [patent_app_number] => 16/497658 [patent_app_country] => US [patent_app_date] => 2019-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5970 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 353 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16497658 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/497658
Thin film transistor and method for manufacturing the same, array substrate, and display device Apr 11, 2019 Issued
Array ( [id] => 14676635 [patent_doc_number] => 20190237432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => SEMICONDUCTOR PACKAGES [patent_app_type] => utility [patent_app_number] => 16/377352 [patent_app_country] => US [patent_app_date] => 2019-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4893 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16377352 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/377352
Semiconductor packages Apr 7, 2019 Issued
Array ( [id] => 14631305 [patent_doc_number] => 20190229022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => CMOS IMPLEMENTATION OF GERMANIUM AND III-V NANOWIRES AND NANORIBBONS IN GATE-ALL-AROUND ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 16/372272 [patent_app_country] => US [patent_app_date] => 2019-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6417 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16372272 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/372272
CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture Mar 31, 2019 Issued
Array ( [id] => 16280302 [patent_doc_number] => 10763343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Effective junction formation in vertical transistor structures by engineered bottom source/drain epitaxy [patent_app_type] => utility [patent_app_number] => 16/369990 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7402 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16369990 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/369990
Effective junction formation in vertical transistor structures by engineered bottom source/drain epitaxy Mar 28, 2019 Issued
Array ( [id] => 14631667 [patent_doc_number] => 20190229204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => EFFECTIVE JUNCTION FORMATION IN VERTICAL TRANSISTOR STRUCTURES BY ENGINEERED BOTTOM SOURCE/DRAIN EPITAXY [patent_app_type] => utility [patent_app_number] => 16/369921 [patent_app_country] => US [patent_app_date] => 2019-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7402 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16369921 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/369921
EFFECTIVE JUNCTION FORMATION IN VERTICAL TRANSISTOR STRUCTURES BY ENGINEERED BOTTOM SOURCE/DRAIN EPITAXY Mar 28, 2019 Abandoned
Array ( [id] => 15580765 [patent_doc_number] => 10580776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Memory arrays [patent_app_type] => utility [patent_app_number] => 16/368361 [patent_app_country] => US [patent_app_date] => 2019-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 6187 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16368361 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/368361
Memory arrays Mar 27, 2019 Issued
Array ( [id] => 16308743 [patent_doc_number] => 10777553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Integrated circuit device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/363050 [patent_app_country] => US [patent_app_date] => 2019-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 13555 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16363050 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/363050
Integrated circuit device and method of manufacturing the same Mar 24, 2019 Issued
Array ( [id] => 17284175 [patent_doc_number] => 11201219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-14 [patent_title] => Integrated circuit device and method of manufacturing integrated circuit device [patent_app_type] => utility [patent_app_number] => 16/492342 [patent_app_country] => US [patent_app_date] => 2019-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 11393 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16492342 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/492342
Integrated circuit device and method of manufacturing integrated circuit device Mar 11, 2019 Issued
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