Search

John J. Figueroa

Examiner (ID: 15617, Phone: (571)272-8916 , Office: P/1768 )

Most Active Art Unit
1768
Art Unit(s)
1768, 1772, 1796, 1763, 1712, 1765
Total Applications
1556
Issued Applications
1186
Pending Applications
112
Abandoned Applications
275

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12477858 [patent_doc_number] => 09991207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Test key strcutures, integrated circuit packages and methods of forming the same [patent_app_type] => utility [patent_app_number] => 15/162630 [patent_app_country] => US [patent_app_date] => 2016-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 26 [patent_no_of_words] => 7529 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15162630 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/162630
Test key strcutures, integrated circuit packages and methods of forming the same May 23, 2016 Issued
Array ( [id] => 11071543 [patent_doc_number] => 20160268507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'Resistance Variable Memory Structure and Method of Forming the Same' [patent_app_type] => utility [patent_app_number] => 15/161443 [patent_app_country] => US [patent_app_date] => 2016-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15161443 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/161443
Resistance variable memory structure and method of forming the same May 22, 2016 Issued
Array ( [id] => 11315682 [patent_doc_number] => 20160351792 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'MAGNETIC SHIELDING FOR MTJ DEVICE OR BIT' [patent_app_type] => utility [patent_app_number] => 15/162594 [patent_app_country] => US [patent_app_date] => 2016-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 15238 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15162594 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/162594
Magnetic shielding for MTJ device or bit May 22, 2016 Issued
Array ( [id] => 13485605 [patent_doc_number] => 20180294345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-11 [patent_title] => METHOD OF FORMING GATE-ALL-AROUND STRUCTURES [patent_app_type] => utility [patent_app_number] => 15/765490 [patent_app_country] => US [patent_app_date] => 2016-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2604 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15765490 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/765490
Method of forming gate-all-around structures May 16, 2016 Issued
Array ( [id] => 11043734 [patent_doc_number] => 20160240690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/137621 [patent_app_country] => US [patent_app_date] => 2016-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 23923 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15137621 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/137621
SEMICONDUCTOR DEVICE Apr 24, 2016 Abandoned
Array ( [id] => 11036356 [patent_doc_number] => 20160233312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-11 [patent_title] => 'FRINGE CAPACITANCE REDUCTION FOR REPLACEMENT GATE CMOS' [patent_app_type] => utility [patent_app_number] => 15/093881 [patent_app_country] => US [patent_app_date] => 2016-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1932 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15093881 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/093881
Fringe capacitance reduction for replacement gate CMOS Apr 7, 2016 Issued
Array ( [id] => 12012940 [patent_doc_number] => 09806265 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-31 [patent_title] => 'Heterogeneous nanostructures for hierarchal assembly' [patent_app_type] => utility [patent_app_number] => 15/092894 [patent_app_country] => US [patent_app_date] => 2016-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4806 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15092894 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/092894
Heterogeneous nanostructures for hierarchal assembly Apr 6, 2016 Issued
Array ( [id] => 12516234 [patent_doc_number] => 10002879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-19 [patent_title] => Semiconductor structure having gate replacement and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/092856 [patent_app_country] => US [patent_app_date] => 2016-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 2099 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15092856 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/092856
Semiconductor structure having gate replacement and method for manufacturing the same Apr 6, 2016 Issued
Array ( [id] => 11273893 [patent_doc_number] => 20160336440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'SUPER JUNCTION DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/092607 [patent_app_country] => US [patent_app_date] => 2016-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3317 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15092607 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/092607
SUPER JUNCTION DEVICE AND METHOD OF MANUFACTURING THE SAME Apr 5, 2016 Abandoned
Array ( [id] => 11984511 [patent_doc_number] => 20170288666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'VOLTAGE-CONTROLLED MAGNETIC-BASED DEVICES HAVING TOPOLOGICAL INSULATOR/MAGNETIC INSULATOR HETEROSTRUCTURE' [patent_app_type] => utility [patent_app_number] => 15/087244 [patent_app_country] => US [patent_app_date] => 2016-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2781 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15087244 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/087244
Voltage-controlled magnetic-based devices having topological insulator/magnetic insulator heterostructure Mar 30, 2016 Issued
Array ( [id] => 11014283 [patent_doc_number] => 20160211236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/082379 [patent_app_country] => US [patent_app_date] => 2016-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6754 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15082379 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/082379
SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME Mar 27, 2016 Abandoned
Array ( [id] => 11007301 [patent_doc_number] => 20160204252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/073574 [patent_app_country] => US [patent_app_date] => 2016-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 38751 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15073574 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/073574
Semiconductor device Mar 16, 2016 Issued
Array ( [id] => 11007224 [patent_doc_number] => 20160204176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/072486 [patent_app_country] => US [patent_app_date] => 2016-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6583 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15072486 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/072486
DISPLAY DEVICE Mar 16, 2016 Abandoned
Array ( [id] => 12478299 [patent_doc_number] => 09991355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Implantation formed metal-insulator-semiconductor (MIS) contacts [patent_app_type] => utility [patent_app_number] => 15/068973 [patent_app_country] => US [patent_app_date] => 2016-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2422 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15068973 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/068973
Implantation formed metal-insulator-semiconductor (MIS) contacts Mar 13, 2016 Issued
Array ( [id] => 12498942 [patent_doc_number] => 09997609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => Implantation formed metal-insulator-semiconductor (MIS) contacts [patent_app_type] => utility [patent_app_number] => 15/068958 [patent_app_country] => US [patent_app_date] => 2016-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2422 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15068958 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/068958
Implantation formed metal-insulator-semiconductor (MIS) contacts Mar 13, 2016 Issued
Array ( [id] => 13006425 [patent_doc_number] => 10026889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Semiconductor structures and devices and methods of forming semiconductor structures and magnetic memory cells [patent_app_type] => utility [patent_app_number] => 15/057909 [patent_app_country] => US [patent_app_date] => 2016-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 29 [patent_no_of_words] => 17513 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15057909 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/057909
Semiconductor structures and devices and methods of forming semiconductor structures and magnetic memory cells Feb 29, 2016 Issued
Array ( [id] => 10826066 [patent_doc_number] => 20160172234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'METHOD OF FORMING A SEMICONDUCTOR DEVICE INCLUDING TRENCH TERMINATION AND TRENCH STRUCTURE THEREFOR' [patent_app_type] => utility [patent_app_number] => 15/047874 [patent_app_country] => US [patent_app_date] => 2016-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12479 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15047874 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/047874
Method of forming a semiconductor device including trench termination Feb 18, 2016 Issued
Array ( [id] => 15955327 [patent_doc_number] => 10665579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Chip package assembly with power management integrated circuit and integrated circuit die [patent_app_type] => utility [patent_app_number] => 15/045228 [patent_app_country] => US [patent_app_date] => 2016-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4575 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15045228 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/045228
Chip package assembly with power management integrated circuit and integrated circuit die Feb 15, 2016 Issued
Array ( [id] => 10787677 [patent_doc_number] => 20160133833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-12 [patent_title] => 'REPLACEMENT CONDUCTIVE HARD MASK FOR MULTI-STEP MAGNETIC TUNNEL JUNCTION (MTJ) ETCH' [patent_app_type] => utility [patent_app_number] => 14/995193 [patent_app_country] => US [patent_app_date] => 2016-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7094 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14995193 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/995193
REPLACEMENT CONDUCTIVE HARD MASK FOR MULTI-STEP MAGNETIC TUNNEL JUNCTION (MTJ) ETCH Jan 12, 2016 Abandoned
Array ( [id] => 12089070 [patent_doc_number] => 09842804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-12 [patent_title] => 'Methods for reducing dual damascene distortion' [patent_app_type] => utility [patent_app_number] => 14/986855 [patent_app_country] => US [patent_app_date] => 2016-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5230 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14986855 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/986855
Methods for reducing dual damascene distortion Jan 3, 2016 Issued
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