Search

John J. Figueroa

Examiner (ID: 15617, Phone: (571)272-8916 , Office: P/1768 )

Most Active Art Unit
1768
Art Unit(s)
1768, 1772, 1796, 1763, 1712, 1765
Total Applications
1556
Issued Applications
1186
Pending Applications
112
Abandoned Applications
275

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16660703 [patent_doc_number] => 20210057340 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-25 [patent_title] => Methods for Reducing Dual Damascene Distortion [patent_app_type] => utility [patent_app_number] => 17/077556 [patent_app_country] => US [patent_app_date] => 2020-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5089 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17077556 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/077556
Methods for reducing dual damascene distortion Oct 21, 2020 Issued
Array ( [id] => 17908701 [patent_doc_number] => 11462564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Manufacturing method of a semiconductor device [patent_app_type] => utility [patent_app_number] => 17/076193 [patent_app_country] => US [patent_app_date] => 2020-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 35 [patent_no_of_words] => 11879 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17076193 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/076193
Manufacturing method of a semiconductor device Oct 20, 2020 Issued
Array ( [id] => 17551573 [patent_doc_number] => 20220122915 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/073413 [patent_app_country] => US [patent_app_date] => 2020-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2629 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17073413 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/073413
SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF Oct 18, 2020 Abandoned
Array ( [id] => 17716584 [patent_doc_number] => 11380582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Semiconductor structure and method for forming ihe same [patent_app_type] => utility [patent_app_number] => 17/061185 [patent_app_country] => US [patent_app_date] => 2020-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4165 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17061185 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/061185
Semiconductor structure and method for forming ihe same Sep 30, 2020 Issued
Array ( [id] => 16586170 [patent_doc_number] => 20210020572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/061141 [patent_app_country] => US [patent_app_date] => 2020-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 43048 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17061141 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/061141
Semiconductor device and method of manufacturing the same Sep 30, 2020 Issued
Array ( [id] => 16578746 [patent_doc_number] => 20210013147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => ELECTRONIC DEVICE WITH SHORT CIRCUIT PROTECTION ELEMENT, FABRICATION METHOD AND DESIGN METHOD [patent_app_type] => utility [patent_app_number] => 17/036312 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3525 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17036312 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/036312
Electronic device with short circuit protection element, fabrication method and design method Sep 28, 2020 Issued
Array ( [id] => 18000923 [patent_doc_number] => 11502034 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Semiconductor devices with backside power rail and methods of fabrication thereof [patent_app_type] => utility [patent_app_number] => 17/027344 [patent_app_country] => US [patent_app_date] => 2020-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 64 [patent_figures_cnt] => 114 [patent_no_of_words] => 13917 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17027344 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/027344
Semiconductor devices with backside power rail and methods of fabrication thereof Sep 20, 2020 Issued
Array ( [id] => 16723856 [patent_doc_number] => 20210091003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/018838 [patent_app_country] => US [patent_app_date] => 2020-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6299 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17018838 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/018838
Semiconductor memory device Sep 10, 2020 Issued
Array ( [id] => 17463753 [patent_doc_number] => 20220077059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-10 [patent_title] => INTERCONNECT STRUCTURE IN SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/017596 [patent_app_country] => US [patent_app_date] => 2020-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10925 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17017596 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/017596
Interconnect structure in semiconductor device and method of forming the same Sep 9, 2020 Issued
Array ( [id] => 17448205 [patent_doc_number] => 20220068710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => SEMICONDUCTOR DEVICE WITH INTERVENING LAYER AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/004902 [patent_app_country] => US [patent_app_date] => 2020-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17004902 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/004902
Semiconductor device with intervening layer and method for fabricating the same Aug 26, 2020 Issued
Array ( [id] => 17825782 [patent_doc_number] => 11430736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Semiconductor device including having metal organic framework interlayer dielectric layer between metal lines and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/000934 [patent_app_country] => US [patent_app_date] => 2020-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 77 [patent_no_of_words] => 20602 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17000934 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/000934
Semiconductor device including having metal organic framework interlayer dielectric layer between metal lines and methods of forming the same Aug 23, 2020 Issued
Array ( [id] => 17431696 [patent_doc_number] => 20220059405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => Bottom Lateral Expansion of Contact Plugs Through Implantation [patent_app_type] => utility [patent_app_number] => 17/001247 [patent_app_country] => US [patent_app_date] => 2020-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8048 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17001247 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/001247
Bottom lateral expansion of contact plugs through implantation Aug 23, 2020 Issued
Array ( [id] => 17878542 [patent_doc_number] => 11450565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Ion implant process for defect elimination in metal layer planarization [patent_app_type] => utility [patent_app_number] => 16/997616 [patent_app_country] => US [patent_app_date] => 2020-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6430 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16997616 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/997616
Ion implant process for defect elimination in metal layer planarization Aug 18, 2020 Issued
Array ( [id] => 17700353 [patent_doc_number] => 11374088 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Leakage reduction in gate-all-around devices [patent_app_type] => utility [patent_app_number] => 16/994274 [patent_app_country] => US [patent_app_date] => 2020-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 34 [patent_no_of_words] => 14101 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16994274 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/994274
Leakage reduction in gate-all-around devices Aug 13, 2020 Issued
Array ( [id] => 18205470 [patent_doc_number] => 11587875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Connecting structure and method for forming the same [patent_app_type] => utility [patent_app_number] => 16/990940 [patent_app_country] => US [patent_app_date] => 2020-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7313 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16990940 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/990940
Connecting structure and method for forming the same Aug 10, 2020 Issued
Array ( [id] => 17402924 [patent_doc_number] => 20220045015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => NAND FLASH BLOCK ARCHITECTURE ENHANCEMENT TO PREVENT BLOCK LIFTING [patent_app_type] => utility [patent_app_number] => 16/984962 [patent_app_country] => US [patent_app_date] => 2020-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8211 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16984962 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/984962
NAND flash block architecture enhancement to prevent block lifting Aug 3, 2020 Issued
Array ( [id] => 16456175 [patent_doc_number] => 20200365601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => STRUCTURES AND SRAM BIT CELLS INTEGRATING COMPLEMENTARY FIELD-EFFECT TRANSISTORS [patent_app_type] => utility [patent_app_number] => 16/984468 [patent_app_country] => US [patent_app_date] => 2020-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7143 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16984468 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/984468
Structures and SRAM bit cells integrating complementary field-effect transistors Aug 3, 2020 Issued
Array ( [id] => 17863037 [patent_doc_number] => 11444199 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-13 [patent_title] => Method of manufacturing a semiconductor device and a semiconductor device [patent_app_type] => utility [patent_app_number] => 16/984075 [patent_app_country] => US [patent_app_date] => 2020-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 9312 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16984075 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/984075
Method of manufacturing a semiconductor device and a semiconductor device Aug 2, 2020 Issued
Array ( [id] => 16723855 [patent_doc_number] => 20210091002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/936656 [patent_app_country] => US [patent_app_date] => 2020-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13878 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16936656 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/936656
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE Jul 22, 2020 Abandoned
Array ( [id] => 17373931 [patent_doc_number] => 20220028983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => Source/Drain Contact Structure [patent_app_type] => utility [patent_app_number] => 16/935686 [patent_app_country] => US [patent_app_date] => 2020-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7128 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16935686 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/935686
Source/drain contact structure Jul 21, 2020 Issued
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