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John J. Tabone Jr.

Examiner (ID: 1826, Phone: (571)272-3827 , Office: P/2117 )

Most Active Art Unit
2111
Art Unit(s)
2117, 2138, 2111, 2133
Total Applications
1411
Issued Applications
1231
Pending Applications
51
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20096982 [patent_doc_number] => 20250226918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => POLAR CODING SYSTEMS, PROCEDURES, AND SIGNALING [patent_app_type] => utility [patent_app_number] => 19/065495 [patent_app_country] => US [patent_app_date] => 2025-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19065495 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/065495
POLAR CODING SYSTEMS, PROCEDURES, AND SIGNALING Feb 26, 2025 Pending
Array ( [id] => 20026332 [patent_doc_number] => 20250164554 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => SYSTEM AND METHOD FOR FAULT SEQUENCE RECORDING [patent_app_type] => utility [patent_app_number] => 19/024722 [patent_app_country] => US [patent_app_date] => 2025-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19024722 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/024722
SYSTEM AND METHOD FOR FAULT SEQUENCE RECORDING Jan 15, 2025 Pending
Array ( [id] => 20027122 [patent_doc_number] => 20250165344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => Storage System Parity Based On System Characteristics [patent_app_type] => utility [patent_app_number] => 19/023090 [patent_app_country] => US [patent_app_date] => 2025-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26533 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19023090 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/023090
Storage System Parity Based On System Characteristics Jan 14, 2025 Pending
Array ( [id] => 20011875 [patent_doc_number] => 20250150097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => CHANNEL CODING METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 19/017023 [patent_app_country] => US [patent_app_date] => 2025-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13335 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19017023 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/017023
CHANNEL CODING METHOD AND APPARATUS Jan 9, 2025 Pending
Array ( [id] => 20812067 [patent_doc_number] => 20260186893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-07-02 [patent_title] => Latch-Based Low-Density Parity Check (LDPC) Implementations [patent_app_type] => utility [patent_app_number] => 19/002482 [patent_app_country] => US [patent_app_date] => 2024-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5972 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19002482 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/002482
Latch-Based Low-Density Parity Check (LDPC) Implementations Dec 25, 2024 Pending
Array ( [id] => 20089825 [patent_doc_number] => 20250219761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => APPARATUS AND METHOD OF SCHEDULING AND OPERATING PROCESSORS FOR DECODING FORWARD ERROR CORRECTION CODEWORDS [patent_app_type] => utility [patent_app_number] => 19/001780 [patent_app_country] => US [patent_app_date] => 2024-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19001780 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/001780
APPARATUS AND METHOD OF SCHEDULING AND OPERATING PROCESSORS FOR DECODING FORWARD ERROR CORRECTION CODEWORDS Dec 25, 2024 Pending
Array ( [id] => 19985704 [patent_doc_number] => 20250123926 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => Data Reconstruction Method and Apparatus [patent_app_type] => utility [patent_app_number] => 18/989694 [patent_app_country] => US [patent_app_date] => 2024-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18989694 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/989694
Data Reconstruction Method and Apparatus Dec 19, 2024 Pending
Array ( [id] => 19893926 [patent_doc_number] => 20250119238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => PHYSICAL LAYER PROTOCOL DATA UNIT-BASED COMMUNICATION METHOD AND APPARATUS [patent_app_type] => utility [patent_app_number] => 18/984157 [patent_app_country] => US [patent_app_date] => 2024-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 35184 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18984157 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/984157
PHYSICAL LAYER PROTOCOL DATA UNIT-BASED COMMUNICATION METHOD AND APPARATUS Dec 16, 2024 Pending
Array ( [id] => 20062196 [patent_doc_number] => 20250200418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => QUANTUM ENCODING CIRCUIT FOR 5-QUBIT ERROR CORRECTING CODE [patent_app_type] => utility [patent_app_number] => 18/979764 [patent_app_country] => US [patent_app_date] => 2024-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18979764 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/979764
QUANTUM ENCODING CIRCUIT FOR 5-QUBIT ERROR CORRECTING CODE Dec 12, 2024 Pending
Array ( [id] => 19863783 [patent_doc_number] => 20250102569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => 3D TAP & SCAN PORT ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/973377 [patent_app_country] => US [patent_app_date] => 2024-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 351 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18973377 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/973377
3D TAP & SCAN PORT ARCHITECTURES Dec 8, 2024 Pending
Array ( [id] => 20052070 [patent_doc_number] => 20250190292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => MULTIVARIATE TIME SERIES ANOMALY DETECTION [patent_app_type] => utility [patent_app_number] => 18/973018 [patent_app_country] => US [patent_app_date] => 2024-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3412 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18973018 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/973018
MULTIVARIATE TIME SERIES ANOMALY DETECTION Dec 7, 2024 Pending
Array ( [id] => 20060848 [patent_doc_number] => 20250199070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => SCAN FLIP-FLOP [patent_app_type] => utility [patent_app_number] => 18/971585 [patent_app_country] => US [patent_app_date] => 2024-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1093 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18971585 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/971585
SCAN FLIP-FLOP Dec 5, 2024 Pending
Array ( [id] => 20087296 [patent_doc_number] => 20250217232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => APPARATUSES AND METHODS FOR ALIASING IN DEVICE LEVEL ERROR CORRECTION BASED ON MODULE LEVEL ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 18/972361 [patent_app_country] => US [patent_app_date] => 2024-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3983 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18972361 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/972361
APPARATUSES AND METHODS FOR ALIASING IN DEVICE LEVEL ERROR CORRECTION BASED ON MODULE LEVEL ERROR CORRECTION Dec 5, 2024 Pending
Array ( [id] => 19851467 [patent_doc_number] => 20250096818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => ACCELERATED ERASURE CODING SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 18/968656 [patent_app_country] => US [patent_app_date] => 2024-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16471 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18968656 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/968656
ACCELERATED ERASURE CODING SYSTEM AND METHOD Dec 3, 2024 Pending
Array ( [id] => 20037153 [patent_doc_number] => 20250175375 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => NR Broadcast Channel Transmission [patent_app_type] => utility [patent_app_number] => 18/966858 [patent_app_country] => US [patent_app_date] => 2024-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4133 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18966858 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/966858
NR Broadcast Channel Transmission Dec 2, 2024 Pending
Array ( [id] => 19802572 [patent_doc_number] => 20250068497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => ERROR DETECTION AND CORRECTION METHOD AND CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/948491 [patent_app_country] => US [patent_app_date] => 2024-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8550 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18948491 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/948491
ERROR DETECTION AND CORRECTION METHOD AND CIRCUIT Nov 14, 2024 Pending
Array ( [id] => 19803714 [patent_doc_number] => 20250069639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => MEMORY AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/945527 [patent_app_country] => US [patent_app_date] => 2024-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4399 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18945527 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/945527
Memory and operation method thereof Nov 12, 2024 Issued
Array ( [id] => 19802591 [patent_doc_number] => 20250068516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => ACCESSING ERROR STATISTICS FROM A CIRCUIT HAVING INTEGRATED ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 18/942874 [patent_app_country] => US [patent_app_date] => 2024-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2880 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18942874 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/942874
ACCESSING ERROR STATISTICS FROM A CIRCUIT HAVING INTEGRATED ERROR CORRECTION Nov 10, 2024 Pending
Array ( [id] => 19803033 [patent_doc_number] => 20250068958 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => METHODS AND SYSTEMS FOR QUANTUM ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 18/941895 [patent_app_country] => US [patent_app_date] => 2024-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13094 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18941895 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/941895
METHODS AND SYSTEMS FOR QUANTUM ERROR CORRECTION Nov 7, 2024 Pending
Array ( [id] => 19787344 [patent_doc_number] => 20250061023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => ECC CONFIGURATION IN MEMORIES [patent_app_type] => utility [patent_app_number] => 18/936548 [patent_app_country] => US [patent_app_date] => 2024-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15349 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18936548 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/936548
ECC CONFIGURATION IN MEMORIES Nov 3, 2024 Pending
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