Search

John J. Tabone Jr.

Examiner (ID: 1826, Phone: (571)272-3827 , Office: P/2117 )

Most Active Art Unit
2111
Art Unit(s)
2117, 2138, 2111, 2133
Total Applications
1411
Issued Applications
1231
Pending Applications
51
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17552515 [patent_doc_number] => 20220123858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => METHOD AND APPARATUS FOR CHANNEL ENCODING/DECODING IN A COMMUNICATION OR BROADCASTING SYSTEM [patent_app_type] => utility [patent_app_number] => 17/564531 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26445 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17564531 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/564531
Method and apparatus for channel encoding/decoding in a communication or broadcasting system Dec 28, 2021 Issued
Array ( [id] => 18175662 [patent_doc_number] => 11575388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Method and device in UE and base station for channel coding [patent_app_type] => utility [patent_app_number] => 17/558625 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 16479 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 457 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17558625 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/558625
Method and device in UE and base station for channel coding Dec 21, 2021 Issued
Array ( [id] => 17534741 [patent_doc_number] => 20220113350 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => SEGMENTED ROW REPAIR FOR PROGRAMMABLE LOGIC DEVICES [patent_app_type] => utility [patent_app_number] => 17/559322 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5620 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559322 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/559322
Segmented row repair for programmable logic devices Dec 21, 2021 Issued
Array ( [id] => 17534742 [patent_doc_number] => 20220113351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE [patent_app_type] => utility [patent_app_number] => 17/559444 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4674 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559444 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/559444
Wafer scale testing using a 2 signal JTAG interface Dec 21, 2021 Issued
Array ( [id] => 18248108 [patent_doc_number] => 11604696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-14 [patent_title] => Field programmable gate array (FPGA) for improving reliability of key configuration bitstream by reusing buffer memory [patent_app_type] => utility [patent_app_number] => 17/645314 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3629 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17645314 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/645314
Field programmable gate array (FPGA) for improving reliability of key configuration bitstream by reusing buffer memory Dec 20, 2021 Issued
Array ( [id] => 17839001 [patent_doc_number] => 20220276306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => COMMUNICATION METHOD AND ITS SYSTEM BETWEEN INTERCONNECTED DIE AND DSP/FPGA [patent_app_type] => utility [patent_app_number] => 17/626823 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2196 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17626823 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/626823
COMMUNICATION METHOD AND ITS SYSTEM BETWEEN INTERCONNECTED DIE AND DSP/FPGA Dec 15, 2021 Abandoned
Array ( [id] => 18247644 [patent_doc_number] => 11604223 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-03-14 [patent_title] => Clock control system for scan chains [patent_app_type] => utility [patent_app_number] => 17/644605 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 15655 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17644605 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/644605
Clock control system for scan chains Dec 15, 2021 Issued
Array ( [id] => 18118593 [patent_doc_number] => 11549983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => 3D tap and scan port architectures [patent_app_type] => utility [patent_app_number] => 17/551406 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 45 [patent_no_of_words] => 10174 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17551406 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/551406
3D tap and scan port architectures Dec 14, 2021 Issued
Array ( [id] => 18899448 [patent_doc_number] => 20240014933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => UE PROCESSING LOAD INDICATION [patent_app_type] => utility [patent_app_number] => 18/036600 [patent_app_country] => US [patent_app_date] => 2021-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10952 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18036600 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/036600
UE processing load indication Dec 1, 2021 Issued
Array ( [id] => 18345753 [patent_doc_number] => 20230133863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => TESTER CHANNEL MULTIPLEXING IN TEST EQUIPMENT [patent_app_type] => utility [patent_app_number] => 17/539704 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16238 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17539704 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/539704
Tester channel multiplexing in test equipment Nov 30, 2021 Issued
Array ( [id] => 18136177 [patent_doc_number] => 11561855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Error handling optimization in memory sub-system mapping [patent_app_type] => utility [patent_app_number] => 17/530313 [patent_app_country] => US [patent_app_date] => 2021-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10472 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530313 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/530313
Error handling optimization in memory sub-system mapping Nov 17, 2021 Issued
Array ( [id] => 19079275 [patent_doc_number] => 11948650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Testing circuit, testing device and testing method thereof [patent_app_type] => utility [patent_app_number] => 17/453846 [patent_app_country] => US [patent_app_date] => 2021-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4971 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17453846 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/453846
Testing circuit, testing device and testing method thereof Nov 5, 2021 Issued
Array ( [id] => 17537546 [patent_doc_number] => 20220116155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => ELECTRONIC DEVICE MANAGING COMMUNICATION BUFFER AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/519818 [patent_app_country] => US [patent_app_date] => 2021-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17519818 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/519818
Electronic device managing communication buffer and operating method thereof Nov 4, 2021 Issued
Array ( [id] => 17580270 [patent_doc_number] => 20220137125 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => METHOD AND DEVICE FOR TESTING SYSTEM-ON-CHIP, ELECTRONIC DEVICE USING METHOD, AND COMPUTER READABLE STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 17/517873 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17517873 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/517873
Method and device for testing system-on-chip, electronic device using method, and computer readable storage medium Nov 2, 2021 Issued
Array ( [id] => 19583216 [patent_doc_number] => 12149352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => OpenFEC error marking [patent_app_type] => utility [patent_app_number] => 18/036636 [patent_app_country] => US [patent_app_date] => 2021-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4089 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18036636 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/036636
OpenFEC error marking Nov 1, 2021 Issued
Array ( [id] => 18072233 [patent_doc_number] => 11531064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Method for testing a digital electronic circuit to be tested, corresponding test system and computer program product [patent_app_type] => utility [patent_app_number] => 17/514568 [patent_app_country] => US [patent_app_date] => 2021-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7620 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17514568 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/514568
Method for testing a digital electronic circuit to be tested, corresponding test system and computer program product Oct 28, 2021 Issued
Array ( [id] => 18606728 [patent_doc_number] => 11748193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-05 [patent_title] => Electronic circuit with local configuration checkers with unique ID codes [patent_app_type] => utility [patent_app_number] => 17/512853 [patent_app_country] => US [patent_app_date] => 2021-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6287 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17512853 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/512853
Electronic circuit with local configuration checkers with unique ID codes Oct 27, 2021 Issued
Array ( [id] => 20563947 [patent_doc_number] => 12566554 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-03 [patent_title] => Managing data storage in a communications system [patent_app_type] => utility [patent_app_number] => 18/701331 [patent_app_country] => US [patent_app_date] => 2021-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 7992 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18701331 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/701331
Managing data storage in a communications system Oct 14, 2021 Issued
Array ( [id] => 18702567 [patent_doc_number] => 11789074 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Parameter space reduction for device testing [patent_app_type] => utility [patent_app_number] => 17/500639 [patent_app_country] => US [patent_app_date] => 2021-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 10900 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17500639 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/500639
Parameter space reduction for device testing Oct 12, 2021 Issued
Array ( [id] => 17372183 [patent_doc_number] => 20220027235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => PAYLOAD DISTRIBUTION IN SOLID STATE DRIVES [patent_app_type] => utility [patent_app_number] => 17/496933 [patent_app_country] => US [patent_app_date] => 2021-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11807 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496933 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/496933
Payload distribution in solid state drives Oct 7, 2021 Issued
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