Search

John J. Tabone Jr.

Examiner (ID: 1826, Phone: (571)272-3827 , Office: P/2117 )

Most Active Art Unit
2111
Art Unit(s)
2117, 2138, 2111, 2133
Total Applications
1411
Issued Applications
1231
Pending Applications
51
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17621927 [patent_doc_number] => 11340983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-24 [patent_title] => Error code calculation on sensing circuitry [patent_app_type] => utility [patent_app_number] => 17/201970 [patent_app_country] => US [patent_app_date] => 2021-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 10486 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17201970 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/201970
Error code calculation on sensing circuitry Mar 14, 2021 Issued
Array ( [id] => 18290798 [patent_doc_number] => 11619667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-04 [patent_title] => Enhanced loopback diagnostic systems and methods [patent_app_type] => utility [patent_app_number] => 17/195342 [patent_app_country] => US [patent_app_date] => 2021-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17195342 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/195342
Enhanced loopback diagnostic systems and methods Mar 7, 2021 Issued
Array ( [id] => 17339212 [patent_doc_number] => 20220005543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => MEMORY SYSTEM AND MANAGEMENT METHOD OF CHARACTERISTIC INFORMATION OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/190906 [patent_app_country] => US [patent_app_date] => 2021-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6643 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17190906 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/190906
Memory system and management method of characteristic information of semiconductor device Mar 2, 2021 Issued
Array ( [id] => 17400967 [patent_doc_number] => 20220043057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => MONITORING OF INTERCONNECT LINES [patent_app_type] => utility [patent_app_number] => 17/188058 [patent_app_country] => US [patent_app_date] => 2021-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6547 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17188058 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/188058
Monitoring of interconnect lines Feb 28, 2021 Issued
Array ( [id] => 17415843 [patent_doc_number] => 20220050747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-17 [patent_title] => USING OVER PROVISIONING SPACE FOR SELECTIVELY STORING BLOCK PARITY [patent_app_type] => utility [patent_app_number] => 17/184422 [patent_app_country] => US [patent_app_date] => 2021-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13233 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184422 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/184422
Using over provisioning space for selectively storing block parity Feb 23, 2021 Issued
Array ( [id] => 18072751 [patent_doc_number] => 11531585 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Memory module and operating method [patent_app_type] => utility [patent_app_number] => 17/177415 [patent_app_country] => US [patent_app_date] => 2021-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6497 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17177415 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/177415
Memory module and operating method Feb 16, 2021 Issued
Array ( [id] => 17824533 [patent_doc_number] => 11429481 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-30 [patent_title] => Restoring memory data integrity [patent_app_type] => utility [patent_app_number] => 17/178207 [patent_app_country] => US [patent_app_date] => 2021-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7551 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17178207 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/178207
Restoring memory data integrity Feb 16, 2021 Issued
Array ( [id] => 17024163 [patent_doc_number] => 20210248034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => MEMORY CONTROLLER AND FLASH MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/161899 [patent_app_country] => US [patent_app_date] => 2021-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10888 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17161899 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/161899
Memory controller and flash memory system Jan 28, 2021 Issued
Array ( [id] => 17999617 [patent_doc_number] => 11500724 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-15 [patent_title] => Flexible parity information for storage systems [patent_app_type] => utility [patent_app_number] => 17/160624 [patent_app_country] => US [patent_app_date] => 2021-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 31455 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17160624 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/160624
Flexible parity information for storage systems Jan 27, 2021 Issued
Array ( [id] => 17878377 [patent_doc_number] => 11450398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Method of testing slave device of inter-integrated circuit bus [patent_app_type] => utility [patent_app_number] => 17/156679 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4111 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17156679 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/156679
Method of testing slave device of inter-integrated circuit bus Jan 24, 2021 Issued
Array ( [id] => 17750903 [patent_doc_number] => 20220229108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => IDENTIFYING DATA VALID WINDOWS [patent_app_type] => utility [patent_app_number] => 17/153726 [patent_app_country] => US [patent_app_date] => 2021-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10034 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17153726 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/153726
Identifying data valid windows Jan 19, 2021 Issued
Array ( [id] => 16811830 [patent_doc_number] => 20210134385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => MANAGEMENT OF TEST RESOURCES TO PERFORM TESTING OF MEMORY COMPONENTS UNDER DIFFERENT TEMPERATURE CONDITIONS [patent_app_type] => utility [patent_app_number] => 17/147072 [patent_app_country] => US [patent_app_date] => 2021-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10577 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17147072 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/147072
Management of test resources to perform testing of memory components under different temperature conditions Jan 11, 2021 Issued
Array ( [id] => 17940255 [patent_doc_number] => 11474708 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Memory system for handling a bad block and operation method thereof [patent_app_type] => utility [patent_app_number] => 17/144534 [patent_app_country] => US [patent_app_date] => 2021-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14784 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17144534 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/144534
Memory system for handling a bad block and operation method thereof Jan 7, 2021 Issued
Array ( [id] => 17572220 [patent_doc_number] => 11320485 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-03 [patent_title] => Scan wrapper architecture for system-on-chip [patent_app_type] => utility [patent_app_number] => 17/247948 [patent_app_country] => US [patent_app_date] => 2020-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11593 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17247948 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/247948
Scan wrapper architecture for system-on-chip Dec 30, 2020 Issued
Array ( [id] => 17745462 [patent_doc_number] => 11393541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Mitigating a voltage condition of a memory cell in a memory sub-system [patent_app_type] => utility [patent_app_number] => 17/129627 [patent_app_country] => US [patent_app_date] => 2020-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8050 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17129627 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/129627
Mitigating a voltage condition of a memory cell in a memory sub-system Dec 20, 2020 Issued
Array ( [id] => 17954512 [patent_doc_number] => 11480613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Method and/or system for testing devices in non-secured environment [patent_app_type] => utility [patent_app_number] => 17/127846 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4590 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17127846 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/127846
Method and/or system for testing devices in non-secured environment Dec 17, 2020 Issued
Array ( [id] => 17038283 [patent_doc_number] => 20210255242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => FAILURE DIAGNOSTIC APPARATUS AND FAILURE DIAGNOSTIC METHOD [patent_app_type] => utility [patent_app_number] => 17/121211 [patent_app_country] => US [patent_app_date] => 2020-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9724 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 417 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17121211 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/121211
Failure diagnostic apparatus and failure diagnostic method Dec 13, 2020 Issued
Array ( [id] => 16886810 [patent_doc_number] => 20210173006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-10 [patent_title] => TRUE SINGLE PHASE CLOCK (TSPC) PRE-CHARGE BASED FLIP-FLOP [patent_app_type] => utility [patent_app_number] => 17/117544 [patent_app_country] => US [patent_app_date] => 2020-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 35683 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17117544 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/117544
True single phase clock (TSPC) pre-charge based flip-flop Dec 9, 2020 Issued
Array ( [id] => 17659270 [patent_doc_number] => 20220179735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => MODIFIED CHECKSUM USING A POISON DATA PATTERN [patent_app_type] => utility [patent_app_number] => 17/116143 [patent_app_country] => US [patent_app_date] => 2020-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8394 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17116143 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/116143
Modified checksum using a poison data pattern Dec 8, 2020 Issued
Array ( [id] => 17394246 [patent_doc_number] => 11243253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Wafer scale testing using a 2 signal JTAG interface [patent_app_type] => utility [patent_app_number] => 17/115136 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 4644 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115136 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/115136
Wafer scale testing using a 2 signal JTAG interface Dec 7, 2020 Issued
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