Search

John J. Tabone Jr.

Examiner (ID: 1826, Phone: (571)272-3827 , Office: P/2117 )

Most Active Art Unit
2111
Art Unit(s)
2117, 2138, 2111, 2133
Total Applications
1411
Issued Applications
1231
Pending Applications
51
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17364443 [patent_doc_number] => 11231461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-25 [patent_title] => 3D tap and scan port architectures [patent_app_type] => utility [patent_app_number] => 17/111133 [patent_app_country] => US [patent_app_date] => 2020-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 45 [patent_no_of_words] => 10141 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17111133 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/111133
3D tap and scan port architectures Dec 2, 2020 Issued
Array ( [id] => 16724737 [patent_doc_number] => 20210091884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => METHOD AND APPARATUS FOR CHANNEL ENCODING/DECODING IN A COMMUNICATION OR BROADCASTING SYSTEM [patent_app_type] => utility [patent_app_number] => 17/109476 [patent_app_country] => US [patent_app_date] => 2020-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26237 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -31 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17109476 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/109476
Method and apparatus for channel encoding/decoding in a communication or broadcasting system Dec 1, 2020 Issued
Array ( [id] => 16713815 [patent_doc_number] => 20210080962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => METHOD AND DEVICE IN UE AND BASE STATION FOR CHANNEL CODING [patent_app_type] => utility [patent_app_number] => 17/105659 [patent_app_country] => US [patent_app_date] => 2020-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16461 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 403 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17105659 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/105659
Method and device in UE and base station for channel coding Nov 26, 2020 Issued
Array ( [id] => 17209505 [patent_doc_number] => 11169878 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-09 [patent_title] => Non-volatile memory accessing method using data protection with aid of look-ahead processing, and associated apparatus [patent_app_type] => utility [patent_app_number] => 17/096960 [patent_app_country] => US [patent_app_date] => 2020-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10522 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17096960 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/096960
Non-volatile memory accessing method using data protection with aid of look-ahead processing, and associated apparatus Nov 12, 2020 Issued
Array ( [id] => 18936171 [patent_doc_number] => 11888622 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => HARQ RTT timer adjustment for multi-TB scheduling [patent_app_type] => utility [patent_app_number] => 17/774817 [patent_app_country] => US [patent_app_date] => 2020-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 18351 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17774817 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/774817
HARQ RTT timer adjustment for multi-TB scheduling Nov 4, 2020 Issued
Array ( [id] => 16797003 [patent_doc_number] => 20210126821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-29 [patent_title] => NR Broadcast Channel Transmission [patent_app_type] => utility [patent_app_number] => 17/090352 [patent_app_country] => US [patent_app_date] => 2020-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8909 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17090352 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/090352
NR broadcast channel transmission Nov 4, 2020 Issued
Array ( [id] => 17621926 [patent_doc_number] => 11340982 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-24 [patent_title] => Memory block defect detection and management [patent_app_type] => utility [patent_app_number] => 17/087334 [patent_app_country] => US [patent_app_date] => 2020-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17087334 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/087334
Memory block defect detection and management Nov 1, 2020 Issued
Array ( [id] => 17506632 [patent_doc_number] => 20220099735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => CORE PARTITION CIRCUIT AND TESTING DEVICE [patent_app_type] => utility [patent_app_number] => 17/085019 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5236 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085019 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/085019
Core partition circuit and testing device Oct 29, 2020 Issued
Array ( [id] => 16622844 [patent_doc_number] => 20210041497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => SCAN TEST CONTROL DECODER WITH STORAGE ELEMENTS FOR USE WITHIN INTEGRATED CIRCUIT (IC) DEVICES HAVING LIMITED TEST INTERFACE [patent_app_type] => utility [patent_app_number] => 17/080424 [patent_app_country] => US [patent_app_date] => 2020-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17080424 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/080424
Scan test control decoder with storage elements for use within integrated circuit (IC) devices having limited test interface Oct 25, 2020 Issued
Array ( [id] => 16623534 [patent_doc_number] => 20210042187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => INTER-HAMMING DIFFERENCE ANALYZER FOR MEMORY ARRAY AND MEASURING AND TESTING METHODS FOR INTER-HAMMING DIFFERENCES OF MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 17/077046 [patent_app_country] => US [patent_app_date] => 2020-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7994 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17077046 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/077046
Inter-hamming difference analyzer for memory array and measuring and testing methods for inter-hamming differences of memory array Oct 21, 2020 Issued
Array ( [id] => 17514836 [patent_doc_number] => 11293979 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Method of and an arrangement for analyzing manufacturing defects of multi-chip modules made without known good die [patent_app_type] => utility [patent_app_number] => 17/076496 [patent_app_country] => US [patent_app_date] => 2020-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 28 [patent_no_of_words] => 6225 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17076496 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/076496
Method of and an arrangement for analyzing manufacturing defects of multi-chip modules made without known good die Oct 20, 2020 Issued
Array ( [id] => 16602349 [patent_doc_number] => 20210028880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => MESSAGE CORRECTION AND DYNAMIC CORRECTION ADJUSTMENT FOR COMMUNICATION SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/066907 [patent_app_country] => US [patent_app_date] => 2020-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12897 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17066907 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/066907
Message correction and dynamic correction adjustment for communication systems Oct 8, 2020 Issued
Array ( [id] => 17408255 [patent_doc_number] => 11249134 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-02-15 [patent_title] => Power-collapsible boundary scan [patent_app_type] => utility [patent_app_number] => 17/064220 [patent_app_country] => US [patent_app_date] => 2020-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9629 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17064220 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/064220
Power-collapsible boundary scan Oct 5, 2020 Issued
Array ( [id] => 17527934 [patent_doc_number] => 11300614 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-12 [patent_title] => Save and restore register [patent_app_type] => utility [patent_app_number] => 17/061871 [patent_app_country] => US [patent_app_date] => 2020-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6437 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17061871 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/061871
Save and restore register Oct 1, 2020 Issued
Array ( [id] => 17401618 [patent_doc_number] => 20220043708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => METHOD AND SYSTEM FOR VALIDATING A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/034656 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4804 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17034656 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/034656
Method and system for validating a memory device Sep 27, 2020 Issued
Array ( [id] => 17026173 [patent_doc_number] => 20210250045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => LDPC DECODER, OPERATING METHOD OF LDPC DECODER, AND SEMICONDUCTOR MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/033075 [patent_app_country] => US [patent_app_date] => 2020-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10488 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17033075 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/033075
LDPC decoder, operating method of LDPC decoder, and semiconductor memory system Sep 24, 2020 Issued
Array ( [id] => 17351739 [patent_doc_number] => 11226370 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-01-18 [patent_title] => Recoverable exceptions generation and handling for post-silicon validation [patent_app_type] => utility [patent_app_number] => 17/017663 [patent_app_country] => US [patent_app_date] => 2020-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 3 [patent_no_of_words] => 13853 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17017663 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/017663
Recoverable exceptions generation and handling for post-silicon validation Sep 9, 2020 Issued
Array ( [id] => 16689828 [patent_doc_number] => 20210072305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-11 [patent_title] => ONLINE TEST DATA RECORD AND OFFLINE DATA CONVERSION ANALYSIS SYSTEM, AND METHOD [patent_app_type] => utility [patent_app_number] => 17/013675 [patent_app_country] => US [patent_app_date] => 2020-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3654 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17013675 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/013675
ONLINE TEST DATA RECORD AND OFFLINE DATA CONVERSION ANALYSIS SYSTEM, AND METHOD Sep 6, 2020 Abandoned
Array ( [id] => 17491534 [patent_doc_number] => 11280832 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-03-22 [patent_title] => Memory embedded full scan for latent defects [patent_app_type] => utility [patent_app_number] => 17/013628 [patent_app_country] => US [patent_app_date] => 2020-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4258 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17013628 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/013628
Memory embedded full scan for latent defects Sep 5, 2020 Issued
Array ( [id] => 17381829 [patent_doc_number] => 11239865 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Error correction circuit and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/006525 [patent_app_country] => US [patent_app_date] => 2020-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 14066 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17006525 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/006525
Error correction circuit and operating method thereof Aug 27, 2020 Issued
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