Search

John J. Tabone Jr.

Examiner (ID: 16857, Phone: (571)272-3827 , Office: P/2117 )

Most Active Art Unit
2111
Art Unit(s)
2117, 2138, 2133, 2111
Total Applications
1390
Issued Applications
1219
Pending Applications
42
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15349341 [patent_doc_number] => 20200012562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-09 [patent_title] => ERROR CODE CALCULATION ON SENSING CIRCUITRY [patent_app_type] => utility [patent_app_number] => 16/575061 [patent_app_country] => US [patent_app_date] => 2019-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10448 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16575061 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/575061
Error code calculation on sensing circuitry Sep 17, 2019 Issued
Array ( [id] => 17003231 [patent_doc_number] => 11082062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-03 [patent_title] => Hardware implementations of a quasi-cyclic syndrome decoder [patent_app_type] => utility [patent_app_number] => 16/573102 [patent_app_country] => US [patent_app_date] => 2019-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5297 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16573102 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/573102
Hardware implementations of a quasi-cyclic syndrome decoder Sep 16, 2019 Issued
Array ( [id] => 15371095 [patent_doc_number] => 20200021312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-16 [patent_title] => TRANSMITTING APPARATUS AND SIGNAL PROCESSING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/564934 [patent_app_country] => US [patent_app_date] => 2019-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 39713 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16564934 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/564934
Transmitting apparatus and signal processing method thereof Sep 8, 2019 Issued
Array ( [id] => 17898448 [patent_doc_number] => 20220308110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => UNIVERSAL COMPACTOR ARCHITECTURE FOR TESTING CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/753332 [patent_app_country] => US [patent_app_date] => 2019-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8922 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17753332 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/753332
Universal compactor architecture for testing circuits Sep 5, 2019 Issued
Array ( [id] => 16674723 [patent_doc_number] => 20210063487 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => METHODS AND APPARATUSES TO DETECT TEST PROBE CONTACT AT EXTERNAL TERMINALS [patent_app_type] => utility [patent_app_number] => 16/559511 [patent_app_country] => US [patent_app_date] => 2019-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16559511 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/559511
Methods and apparatuses to detect test probe contact at external terminals Sep 2, 2019 Issued
Array ( [id] => 16788040 [patent_doc_number] => 10990473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-27 [patent_title] => Systems on chips, integrated circuits, and operating methods of the integrated circuits [patent_app_type] => utility [patent_app_number] => 16/555357 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11763 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16555357 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/555357
Systems on chips, integrated circuits, and operating methods of the integrated circuits Aug 28, 2019 Issued
Array ( [id] => 16675695 [patent_doc_number] => 20210064461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => SEMICONDUCTOR DEVICE WITH USER DEFINED OPERATIONS AND ASSOCIATED METHODS AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/554958 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10756 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16554958 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/554958
Semiconductor device with user defined operations and associated methods and systems Aug 28, 2019 Issued
Array ( [id] => 17017150 [patent_doc_number] => 11086791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Methods for supporting mismatched transaction granularities [patent_app_type] => utility [patent_app_number] => 16/555976 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 17428 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16555976 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/555976
Methods for supporting mismatched transaction granularities Aug 28, 2019 Issued
Array ( [id] => 16675702 [patent_doc_number] => 20210064468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => SHARED PARITY PROTECTION [patent_app_type] => utility [patent_app_number] => 16/555014 [patent_app_country] => US [patent_app_date] => 2019-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18269 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16555014 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/555014
Shared parity protection Aug 28, 2019 Issued
Array ( [id] => 16239679 [patent_doc_number] => 20200256913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => APPARATUS AND METHOD AND COMPUTER PROGRAM PRODUCT FOR VERIFYING MEMORY INTERFACE [patent_app_type] => utility [patent_app_number] => 16/548463 [patent_app_country] => US [patent_app_date] => 2019-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5154 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16548463 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/548463
Apparatus and method and computer program product for verifying memory interface Aug 21, 2019 Issued
Array ( [id] => 16833822 [patent_doc_number] => 11010073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Resource sharing in a telecommunications environment [patent_app_type] => utility [patent_app_number] => 16/544003 [patent_app_country] => US [patent_app_date] => 2019-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5323 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16544003 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/544003
Resource sharing in a telecommunications environment Aug 18, 2019 Issued
Array ( [id] => 15219823 [patent_doc_number] => 20190372598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 5/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/542178 [patent_app_country] => US [patent_app_date] => 2019-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16542178 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/542178
Low density parity check encoder having length of 64800 and code rate of 5/15, and low density parity check encoding method using the same Aug 14, 2019 Issued
Array ( [id] => 15219821 [patent_doc_number] => 20190372597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 64800 AND CODE RATE OF 2/15, AND LOW DENSITY PARITY CHECK ENCODING METHOD USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/540991 [patent_app_country] => US [patent_app_date] => 2019-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6443 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16540991 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/540991
Low density parity check encoder having length of 64800 and code rate of 2/15, and low density parity check encoding method using the same Aug 13, 2019 Issued
Array ( [id] => 15184405 [patent_doc_number] => 20190362794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => OPERATION METHOD OF NONVOLATILE MEMORY DEVICE AND STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/539290 [patent_app_country] => US [patent_app_date] => 2019-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18457 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16539290 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/539290
Operation method of nonvolatile memory device and storage device Aug 12, 2019 Issued
Array ( [id] => 16697948 [patent_doc_number] => 10948540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => Integrated protocol analyzer configured within automated test equipment (ate) hardware [patent_app_type] => utility [patent_app_number] => 16/521174 [patent_app_country] => US [patent_app_date] => 2019-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11910 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16521174 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/521174
Integrated protocol analyzer configured within automated test equipment (ate) hardware Jul 23, 2019 Issued
Array ( [id] => 16866518 [patent_doc_number] => 11025278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-01 [patent_title] => Polar coding encoding/decoding method and apparatus [patent_app_type] => utility [patent_app_number] => 16/519988 [patent_app_country] => US [patent_app_date] => 2019-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 15030 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16519988 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/519988
Polar coding encoding/decoding method and apparatus Jul 22, 2019 Issued
Array ( [id] => 16477412 [patent_doc_number] => 10852353 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-01 [patent_title] => Scan test control decoder with storage elements for use within integrated circuit (IC) devices having limited test interface [patent_app_type] => utility [patent_app_number] => 16/460405 [patent_app_country] => US [patent_app_date] => 2019-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5829 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16460405 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/460405
Scan test control decoder with storage elements for use within integrated circuit (IC) devices having limited test interface Jul 1, 2019 Issued
Array ( [id] => 15440145 [patent_doc_number] => 20200034256 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => EFFICIENT RECOVERY OF ERASURE CODED DATA [patent_app_type] => utility [patent_app_number] => 16/460404 [patent_app_country] => US [patent_app_date] => 2019-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16460404 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/460404
Efficient recovery of erasure coded data Jul 1, 2019 Issued
Array ( [id] => 15297477 [patent_doc_number] => 20190391874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => MEMORY STORAGE APPARATUS WITH DYNAMIC DATA REPAIR MECHANISM AND METHOD OF DYNAMIC DATA REPAIR THEREOF [patent_app_type] => utility [patent_app_number] => 16/455769 [patent_app_country] => US [patent_app_date] => 2019-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5285 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16455769 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/455769
Memory storage apparatus with dynamic data repair mechanism and method of dynamic data repair thereof Jun 27, 2019 Issued
Array ( [id] => 14997795 [patent_doc_number] => 20190317855 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-17 [patent_title] => ERROR-CORRECTING CODE MEMORY [patent_app_type] => utility [patent_app_number] => 16/453081 [patent_app_country] => US [patent_app_date] => 2019-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8232 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16453081 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/453081
Error-correcting code memory Jun 25, 2019 Issued
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