Search

John J. Tabone Jr.

Examiner (ID: 18928, Phone: (571)272-3827 , Office: P/2117 )

Most Active Art Unit
2111
Art Unit(s)
2117, 2111, 2138, 2133
Total Applications
1407
Issued Applications
1231
Pending Applications
47
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14123285 [patent_doc_number] => 10248501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Data storage apparatus and operation method thereof [patent_app_type] => utility [patent_app_number] => 15/701718 [patent_app_country] => US [patent_app_date] => 2017-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8273 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15701718 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/701718
Data storage apparatus and operation method thereof Sep 11, 2017 Issued
Array ( [id] => 14493507 [patent_doc_number] => 10333558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Decoding device and decoding method [patent_app_type] => utility [patent_app_number] => 15/702204 [patent_app_country] => US [patent_app_date] => 2017-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 15550 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15702204 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/702204
Decoding device and decoding method Sep 11, 2017 Issued
Array ( [id] => 14298417 [patent_doc_number] => 10289335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Tape drive library integrated memory deduplication [patent_app_type] => utility [patent_app_number] => 15/702158 [patent_app_country] => US [patent_app_date] => 2017-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7648 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15702158 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/702158
Tape drive library integrated memory deduplication Sep 11, 2017 Issued
Array ( [id] => 14917919 [patent_doc_number] => 10430279 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-01 [patent_title] => Dynamic raid expansion [patent_app_type] => utility [patent_app_number] => 15/702557 [patent_app_country] => US [patent_app_date] => 2017-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 15824 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15702557 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/702557
Dynamic raid expansion Sep 11, 2017 Issued
Array ( [id] => 13304455 [patent_doc_number] => 20180203764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-19 [patent_title] => USING PARITY DATA FOR CONCURRENT DATA AUTHENTICATION, CORRECTION, COMPRESSION, AND ENCRYPTION [patent_app_type] => utility [patent_app_number] => 15/701111 [patent_app_country] => US [patent_app_date] => 2017-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29719 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15701111 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/701111
Using parity data for concurrent data authentication, correction, compression, and encryption Sep 10, 2017 Issued
Array ( [id] => 14174245 [patent_doc_number] => 10261127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-16 [patent_title] => Semiconductor integrated circuit [patent_app_type] => utility [patent_app_number] => 15/700975 [patent_app_country] => US [patent_app_date] => 2017-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8947 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15700975 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/700975
Semiconductor integrated circuit Sep 10, 2017 Issued
Array ( [id] => 13377983 [patent_doc_number] => 20180240533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => MEMORY TEST APPARATUS [patent_app_type] => utility [patent_app_number] => 15/693616 [patent_app_country] => US [patent_app_date] => 2017-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7123 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15693616 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/693616
Memory test apparatus Aug 31, 2017 Issued
Array ( [id] => 12289440 [patent_doc_number] => 09933484 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Taps with TO-T2, T4 classes with, without topology selection logic [patent_app_type] => utility [patent_app_number] => 15/691132 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7822 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15691132 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/691132
Taps with TO-T2, T4 classes with, without topology selection logic Aug 29, 2017 Issued
Array ( [id] => 13860163 [patent_doc_number] => 10191801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-29 [patent_title] => Error correction code management of write-once memory codes [patent_app_type] => utility [patent_app_number] => 15/678315 [patent_app_country] => US [patent_app_date] => 2017-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6014 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15678315 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/678315
Error correction code management of write-once memory codes Aug 15, 2017 Issued
Array ( [id] => 12797158 [patent_doc_number] => 20180157555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => MEMORY ARRAY AND MEASURING AND TESTING METHODS FOR INTER-HAMMING DIFFERENCES OF MEMORY ARRAY [patent_app_type] => utility [patent_app_number] => 15/677414 [patent_app_country] => US [patent_app_date] => 2017-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7946 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15677414 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/677414
Memory array and measuring and testing methods for inter-hamming differences of memory array Aug 14, 2017 Issued
Array ( [id] => 15233761 [patent_doc_number] => 10504609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-10 [patent_title] => Semiconductor device and diagnosis method thereof [patent_app_type] => utility [patent_app_number] => 15/658734 [patent_app_country] => US [patent_app_date] => 2017-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 9705 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15658734 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/658734
Semiconductor device and diagnosis method thereof Jul 24, 2017 Issued
Array ( [id] => 12262579 [patent_doc_number] => 20180081775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-22 [patent_title] => 'TEST UNIT AND TEST METHOD FOR EFFICIENT TESTING DURING LONG IDLE PERIODS' [patent_app_type] => utility [patent_app_number] => 15/659257 [patent_app_country] => US [patent_app_date] => 2017-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4309 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15659257 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/659257
Test unit and test method for efficient testing during long idle periods Jul 24, 2017 Issued
Array ( [id] => 12919876 [patent_doc_number] => 20180198468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => ERROR CORRECTION CODE (ECC) DECODERS SHARING LOGIC OPERATIONS, MEMORY CONTROLLERS INCLUDING THE ERROR CORRECTION CODE DECODERS, AND METHODS OF DECODING ERROR CORRECTION CODES [patent_app_type] => utility [patent_app_number] => 15/653730 [patent_app_country] => US [patent_app_date] => 2017-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17839 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15653730 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/653730
Error correction code (ECC) decoders sharing logic operations, memory controllers including the error correction code decoders, and methods of decoding error correction codes Jul 18, 2017 Issued
Array ( [id] => 14739933 [patent_doc_number] => 10389383 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Low-complexity LDPC encoder [patent_app_type] => utility [patent_app_number] => 15/654492 [patent_app_country] => US [patent_app_date] => 2017-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 9832 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15654492 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/654492
Low-complexity LDPC encoder Jul 18, 2017 Issued
Array ( [id] => 14269317 [patent_doc_number] => 10284234 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-07 [patent_title] => Facilitation of data deletion for distributed erasure coding [patent_app_type] => utility [patent_app_number] => 15/654109 [patent_app_country] => US [patent_app_date] => 2017-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7908 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15654109 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/654109
Facilitation of data deletion for distributed erasure coding Jul 18, 2017 Issued
Array ( [id] => 12891874 [patent_doc_number] => 20180189133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => ERROR-CORRECTING CODE MEMORY [patent_app_type] => utility [patent_app_number] => 15/653749 [patent_app_country] => US [patent_app_date] => 2017-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15653749 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/653749
Error-correcting code memory Jul 18, 2017 Issued
Array ( [id] => 12025071 [patent_doc_number] => 20170315170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-02 [patent_title] => 'SCAN RESPONSE REUSE METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/652870 [patent_app_country] => US [patent_app_date] => 2017-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 9522 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15652870 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/652870
Scan path interface with circular shift register, logic, register sets Jul 17, 2017 Issued
Array ( [id] => 12180642 [patent_doc_number] => 20180039578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'DATA STORAGE DEVICE USING HOST MEMORY AND METHOD OF OPERATING SAME' [patent_app_type] => utility [patent_app_number] => 15/652259 [patent_app_country] => US [patent_app_date] => 2017-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7734 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15652259 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/652259
Data storage device using host memory and method of operating same Jul 17, 2017 Issued
Array ( [id] => 14737987 [patent_doc_number] => 10388402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Memory system and memory control method [patent_app_type] => utility [patent_app_number] => 15/648909 [patent_app_country] => US [patent_app_date] => 2017-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15648909 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/648909
Memory system and memory control method Jul 12, 2017 Issued
Array ( [id] => 13345931 [patent_doc_number] => 20180224505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => FLIP-FLOP CIRCUIT AND SCAN CHAIN USING THE SAME [patent_app_type] => utility [patent_app_number] => 15/647485 [patent_app_country] => US [patent_app_date] => 2017-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6689 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15647485 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/647485
Flip-flop circuit and scan chain using the same Jul 11, 2017 Issued
Menu