Search

John J. Tabone Jr.

Examiner (ID: 18928, Phone: (571)272-3827 , Office: P/2117 )

Most Active Art Unit
2111
Art Unit(s)
2117, 2111, 2138, 2133
Total Applications
1407
Issued Applications
1231
Pending Applications
47
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10990478 [patent_doc_number] => 20160187423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'SCAN TOPOLOGY DISCOVERY IN TARGET SYSTEMS' [patent_app_type] => utility [patent_app_number] => 15/065085 [patent_app_country] => US [patent_app_date] => 2016-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8343 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15065085 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/065085
Taps with class T0-T2 and T3, T4(W), and T5(W) capabilities Mar 8, 2016 Issued
Array ( [id] => 11481636 [patent_doc_number] => 09588174 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-03-07 [patent_title] => 'Method for testing through silicon vias in 3D integrated circuits' [patent_app_type] => utility [patent_app_number] => 15/064319 [patent_app_country] => US [patent_app_date] => 2016-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2416 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15064319 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/064319
Method for testing through silicon vias in 3D integrated circuits Mar 7, 2016 Issued
Array ( [id] => 10991484 [patent_doc_number] => 20160188429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'MEMORY CONTROL CIRCUIT, CACHE MEMORY AND MEMORY CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 15/059702 [patent_app_country] => US [patent_app_date] => 2016-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6043 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15059702 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/059702
Memory control circuit, cache memory and memory control method Mar 2, 2016 Issued
Array ( [id] => 10994131 [patent_doc_number] => 20160191077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'MAGIC STATE GENERATION APPARATUS, MAGIC STATE GENERATION METHOD, AND QUANTUM GATE OPERATION METHOD' [patent_app_type] => utility [patent_app_number] => 15/060031 [patent_app_country] => US [patent_app_date] => 2016-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3817 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15060031 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/060031
MAGIC STATE GENERATION APPARATUS, MAGIC STATE GENERATION METHOD, AND QUANTUM GATE OPERATION METHOD Mar 2, 2016 Abandoned
Array ( [id] => 10982445 [patent_doc_number] => 20160179389 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'RESOURCE SHARING IN A TELECOMMUNICATIONS ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 15/046821 [patent_app_country] => US [patent_app_date] => 2016-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5470 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15046821 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/046821
Resource sharing in a telecommunications environment Feb 17, 2016 Issued
Array ( [id] => 11889878 [patent_doc_number] => 09760439 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-12 [patent_title] => 'Using parity data for concurrent data authentication, correction, compression, and encryption' [patent_app_type] => utility [patent_app_number] => 15/018782 [patent_app_country] => US [patent_app_date] => 2016-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 30665 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 557 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15018782 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/018782
Using parity data for concurrent data authentication, correction, compression, and encryption Feb 7, 2016 Issued
Array ( [id] => 11785996 [patent_doc_number] => 09395413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-19 [patent_title] => 'Blocking the effects of scan chain testing upon a change in scan chain topology' [patent_app_type] => utility [patent_app_number] => 15/015790 [patent_app_country] => US [patent_app_date] => 2016-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4873 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15015790 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/015790
Blocking the effects of scan chain testing upon a change in scan chain topology Feb 3, 2016 Issued
Array ( [id] => 11825476 [patent_doc_number] => 20170214413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-27 [patent_title] => 'JOINT SOURCE-CHANNEL CODING WITH DYNAMIC DICTIONARY FOR OBJECT-BASED STORAGE' [patent_app_type] => utility [patent_app_number] => 15/003502 [patent_app_country] => US [patent_app_date] => 2016-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5072 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15003502 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/003502
JOINT SOURCE-CHANNEL CODING WITH DYNAMIC DICTIONARY FOR OBJECT-BASED STORAGE Jan 20, 2016 Abandoned
Array ( [id] => 11020077 [patent_doc_number] => 20160217030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-28 [patent_title] => 'MEMORY SYSTEM AND METHOD OF OPERATING THE MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/001012 [patent_app_country] => US [patent_app_date] => 2016-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 17579 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15001012 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/001012
Memory system and method of operating the memory system Jan 18, 2016 Issued
Array ( [id] => 13084695 [patent_doc_number] => 10062418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-28 [patent_title] => Data programming method and memory storage device [patent_app_type] => utility [patent_app_number] => 14/997575 [patent_app_country] => US [patent_app_date] => 2016-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 13037 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14997575 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/997575
Data programming method and memory storage device Jan 17, 2016 Issued
Array ( [id] => 12228950 [patent_doc_number] => 09916195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-13 [patent_title] => 'Performing a repair operation in arrays' [patent_app_type] => utility [patent_app_number] => 14/993361 [patent_app_country] => US [patent_app_date] => 2016-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5516 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14993361 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/993361
Performing a repair operation in arrays Jan 11, 2016 Issued
Array ( [id] => 11007851 [patent_doc_number] => 20160204803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'DECODING METHOD FOR CONVOLUTIONALLY CODED SIGNAL' [patent_app_type] => utility [patent_app_number] => 14/992269 [patent_app_country] => US [patent_app_date] => 2016-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5029 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14992269 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/992269
Decoding method for convolutionally coded signal Jan 10, 2016 Issued
Array ( [id] => 11731401 [patent_doc_number] => 20170192844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'ERROR CODE CALCULATION ON SENSING CIRCUITRY' [patent_app_type] => utility [patent_app_number] => 14/989264 [patent_app_country] => US [patent_app_date] => 2016-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10732 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14989264 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/989264
Error code calculation on sensing circuitry Jan 5, 2016 Issued
Array ( [id] => 13269067 [patent_doc_number] => 10146618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-04 [patent_title] => Distributed data storage with reduced storage overhead using reduced-dependency erasure codes [patent_app_type] => utility [patent_app_number] => 14/987244 [patent_app_country] => US [patent_app_date] => 2016-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5936 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14987244 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/987244
Distributed data storage with reduced storage overhead using reduced-dependency erasure codes Jan 3, 2016 Issued
Array ( [id] => 11718997 [patent_doc_number] => 20170187497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'FAST COUPLED RETRANSMISSION FOR MULTIPATH COMMUNICATIONS' [patent_app_type] => utility [patent_app_number] => 14/980834 [patent_app_country] => US [patent_app_date] => 2015-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9396 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14980834 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/980834
Fast coupled retransmission for multipath communications Dec 27, 2015 Issued
Array ( [id] => 11563529 [patent_doc_number] => 09626118 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-18 [patent_title] => 'Efficient error handling mechanisms in data storage systems' [patent_app_type] => utility [patent_app_number] => 14/961856 [patent_app_country] => US [patent_app_date] => 2015-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5125 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14961856 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/961856
Efficient error handling mechanisms in data storage systems Dec 6, 2015 Issued
Array ( [id] => 13030389 [patent_doc_number] => 10037817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => Semiconductor memory devices and memory systems including the same [patent_app_type] => utility [patent_app_number] => 14/958149 [patent_app_country] => US [patent_app_date] => 2015-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 30 [patent_no_of_words] => 15027 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14958149 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/958149
Semiconductor memory devices and memory systems including the same Dec 2, 2015 Issued
Array ( [id] => 10731002 [patent_doc_number] => 20160077152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => '3D TAP & SCAN PORT ARCHITECTURES' [patent_app_type] => utility [patent_app_number] => 14/948956 [patent_app_country] => US [patent_app_date] => 2015-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10089 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14948956 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/948956
IC die test, scan, and capture, shift, and update circuitry Nov 22, 2015 Issued
Array ( [id] => 10991460 [patent_doc_number] => 20160188405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'ADAPTIVE ECC TECHNIQUES FOR FLASH MEMORY BASED DATA STORAGE' [patent_app_type] => utility [patent_app_number] => 14/945276 [patent_app_country] => US [patent_app_date] => 2015-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10360 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14945276 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/945276
ADAPTIVE ECC TECHNIQUES FOR FLASH MEMORY BASED DATA STORAGE Nov 17, 2015 Abandoned
Array ( [id] => 10723802 [patent_doc_number] => 20160069949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-10 [patent_title] => 'SEMICONDUCTOR TEST SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/944903 [patent_app_country] => US [patent_app_date] => 2015-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11671 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14944903 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/944903
Semiconductor test system and method Nov 17, 2015 Issued
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