Search

John J. Tabone Jr.

Examiner (ID: 18928, Phone: (571)272-3827 , Office: P/2117 )

Most Active Art Unit
2111
Art Unit(s)
2117, 2111, 2138, 2133
Total Applications
1407
Issued Applications
1231
Pending Applications
47
Abandoned Applications
141

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12013411 [patent_doc_number] => 09806743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-31 [patent_title] => 'System and method of belief propagation decoding' [patent_app_type] => utility [patent_app_number] => 14/941789 [patent_app_country] => US [patent_app_date] => 2015-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 8027 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14941789 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/941789
System and method of belief propagation decoding Nov 15, 2015 Issued
Array ( [id] => 11476690 [patent_doc_number] => 20170063473 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'APPARATUS AND METHOD FOR ELIMINATING IMPULSE INTERFERENCE' [patent_app_type] => utility [patent_app_number] => 14/941795 [patent_app_country] => US [patent_app_date] => 2015-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3580 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14941795 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/941795
Apparatus and method for eliminating impulse interference Nov 15, 2015 Issued
Array ( [id] => 12438687 [patent_doc_number] => 09979416 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-22 [patent_title] => Memory controller and method of data bus inversion using an error detection correction code [patent_app_type] => utility [patent_app_number] => 14/941564 [patent_app_country] => US [patent_app_date] => 2015-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14941564 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/941564
Memory controller and method of data bus inversion using an error detection correction code Nov 13, 2015 Issued
Array ( [id] => 13005659 [patent_doc_number] => 10026500 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Address translation stimuli generation for post-silicon functional validation [patent_app_type] => utility [patent_app_number] => 14/940277 [patent_app_country] => US [patent_app_date] => 2015-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14940277 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/940277
Address translation stimuli generation for post-silicon functional validation Nov 12, 2015 Issued
Array ( [id] => 11924593 [patent_doc_number] => 09792176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-17 [patent_title] => 'Method and apparatus for encoding and decoding data in memory system' [patent_app_type] => utility [patent_app_number] => 14/941051 [patent_app_country] => US [patent_app_date] => 2015-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 21038 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14941051 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/941051
Method and apparatus for encoding and decoding data in memory system Nov 12, 2015 Issued
Array ( [id] => 12201527 [patent_doc_number] => 09904593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-27 [patent_title] => 'Memory device and correction method' [patent_app_type] => utility [patent_app_number] => 14/941126 [patent_app_country] => US [patent_app_date] => 2015-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5009 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14941126 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/941126
Memory device and correction method Nov 12, 2015 Issued
Array ( [id] => 13160931 [patent_doc_number] => 10097203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-09 [patent_title] => Lane-striped computation of packet CRC to maintain burst error properties [patent_app_type] => utility [patent_app_number] => 14/939813 [patent_app_country] => US [patent_app_date] => 2015-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3287 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14939813 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/939813
Lane-striped computation of packet CRC to maintain burst error properties Nov 11, 2015 Issued
Array ( [id] => 10715740 [patent_doc_number] => 20160061887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE' [patent_app_type] => utility [patent_app_number] => 14/934451 [patent_app_country] => US [patent_app_date] => 2015-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4678 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14934451 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/934451
Wafer scale testing using a 2 signal JTAG interface Nov 5, 2015 Issued
Array ( [id] => 10695079 [patent_doc_number] => 20160041224 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'SCAN TOPOLOGY DISCOVERY IN TARGET SYSTEMS' [patent_app_type] => utility [patent_app_number] => 14/918854 [patent_app_country] => US [patent_app_date] => 2015-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8324 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14918854 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/918854
Scan topology discovery in target systems Oct 20, 2015 Issued
Array ( [id] => 10561757 [patent_doc_number] => 09285426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-15 [patent_title] => 'Blocking the effects of scan chain testing upon a change in scan chain topology' [patent_app_type] => utility [patent_app_number] => 14/853077 [patent_app_country] => US [patent_app_date] => 2015-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4845 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14853077 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/853077
Blocking the effects of scan chain testing upon a change in scan chain topology Sep 13, 2015 Issued
Array ( [id] => 11776773 [patent_doc_number] => 09385759 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-05 [patent_title] => 'Accelerated erasure coding system and method' [patent_app_type] => utility [patent_app_number] => 14/852438 [patent_app_country] => US [patent_app_date] => 2015-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 16584 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14852438 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/852438
Accelerated erasure coding system and method Sep 10, 2015 Issued
Array ( [id] => 11253679 [patent_doc_number] => 09479197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-25 [patent_title] => 'Method and apparatus for transmission and reception of in-band on-channel radio signals including complementary low density parity check coding' [patent_app_type] => utility [patent_app_number] => 14/817423 [patent_app_country] => US [patent_app_date] => 2015-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 8030 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14817423 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/817423
Method and apparatus for transmission and reception of in-band on-channel radio signals including complementary low density parity check coding Aug 3, 2015 Issued
Array ( [id] => 10500659 [patent_doc_number] => 09229056 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'IC die top, bottom signals, tap lock, test, scan circuitry' [patent_app_type] => utility [patent_app_number] => 14/816220 [patent_app_country] => US [patent_app_date] => 2015-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 45 [patent_no_of_words] => 10077 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14816220 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/816220
IC die top, bottom signals, tap lock, test, scan circuitry Aug 2, 2015 Issued
Array ( [id] => 10194072 [patent_doc_number] => 09222977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-29 [patent_title] => 'Semiconductor test system and method' [patent_app_type] => utility [patent_app_number] => 14/807214 [patent_app_country] => US [patent_app_date] => 2015-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 34 [patent_no_of_words] => 11637 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14807214 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/807214
Semiconductor test system and method Jul 22, 2015 Issued
Array ( [id] => 12955624 [patent_doc_number] => 09838041 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-05 [patent_title] => Device type differentiation for redundancy coded data storage systems [patent_app_type] => utility [patent_app_number] => 14/742685 [patent_app_country] => US [patent_app_date] => 2015-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 24350 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14742685 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/742685
Device type differentiation for redundancy coded data storage systems Jun 16, 2015 Issued
Array ( [id] => 12536538 [patent_doc_number] => 10009044 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-06-26 [patent_title] => Device type differentiation for redundancy coded data storage systems [patent_app_type] => utility [patent_app_number] => 14/742687 [patent_app_country] => US [patent_app_date] => 2015-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 24350 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14742687 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/742687
Device type differentiation for redundancy coded data storage systems Jun 16, 2015 Issued
Array ( [id] => 12955621 [patent_doc_number] => 09838040 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-05 [patent_title] => Layered data redundancy coding techniques for layer-local data recovery [patent_app_type] => utility [patent_app_number] => 14/741406 [patent_app_country] => US [patent_app_date] => 2015-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 21598 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14741406 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/741406
Layered data redundancy coding techniques for layer-local data recovery Jun 15, 2015 Issued
Array ( [id] => 12955621 [patent_doc_number] => 09838040 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-05 [patent_title] => Layered data redundancy coding techniques for layer-local data recovery [patent_app_type] => utility [patent_app_number] => 14/741406 [patent_app_country] => US [patent_app_date] => 2015-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 21598 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14741406 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/741406
Layered data redundancy coding techniques for layer-local data recovery Jun 15, 2015 Issued
Array ( [id] => 12955621 [patent_doc_number] => 09838040 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-05 [patent_title] => Layered data redundancy coding techniques for layer-local data recovery [patent_app_type] => utility [patent_app_number] => 14/741406 [patent_app_country] => US [patent_app_date] => 2015-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 21598 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14741406 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/741406
Layered data redundancy coding techniques for layer-local data recovery Jun 15, 2015 Issued
Array ( [id] => 12955621 [patent_doc_number] => 09838040 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-05 [patent_title] => Layered data redundancy coding techniques for layer-local data recovery [patent_app_type] => utility [patent_app_number] => 14/741406 [patent_app_country] => US [patent_app_date] => 2015-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 21598 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14741406 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/741406
Layered data redundancy coding techniques for layer-local data recovery Jun 15, 2015 Issued
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